io_lvds_synopsys.vhd

基于VHDL语言的低压差分接口规范的实现

use unisim.vcomponents.all;

entity IOBUFDS_FDPE_LVDS is
  port (
    D, T, CE, C, PRE : in std_logic;
    Q : out std_logic;
    IO, IOB : inout std_logic
  );
end entity IOBUFDS_FDPE_LVDS;

architecture lvds_buff0 of IOBUFDS_FDPE_LVDS is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute off_p IOB "true" -type string
-- set_attribute off_n IOB "true" -type string
-- set_attribute tri_p IOB "true" -type string
-- set_attribute tri_n IOB "true" -type string
-- set_attribute iff_p IOB "true" -type string
-- synopsys dc_script_end
  signal dummy_o, D_n, q_n, q_p, t_p, t_n, i_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDPE port map (D => D, CE => CE, C => C, PRE => PRE, Q => q_p);
  off_n : FDCE port map (D => D_n, CE => CE, C => C, CLR => PRE, Q => q_n);
  tri_p : FDPE port map (D => T, CE => CE, C => C, PRE => PRE, Q => t_p);
  tri_n : FDPE port map (D => T, CE => CE, C => C, PRE => PRE, Q => t_n);
  iff_p : FDPE port map (D => i_p, CE => CE, C => C, PRE => PRE, Q => Q);
  pad_p : IOBUF_LVDS port map (I => q_p, T => t_p, O => i_p, IO => IO);
  pad_n : IOBUF_LVDS port map (I => q_n, T => t_n, O => dummy_o, IO => IOB);
end lvds_buff0; -- IOBUFDS_FDPE_LVDS

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity IOBUFDS_FDR_LVDS is
  port (
    D, T, C, R : in std_logic;
    Q : out std_logic;
    IO, IOB : inout std_logic
  );
end entity IOBUFDS_FDR_LVDS;

architecture lvds_buff0 of IOBUFDS_FDR_LVDS is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute off_p IOB "true" -type string
-- set_attribute off_n IOB "true" -type string
-- set_attribute tri_p IOB "true" -type string
-- set_attribute tri_n IOB "true" -type string
-- set_attribute iff_p IOB "true" -type string
-- synopsys dc_script_end
  signal dummy_o, D_n, q_n, q_p, t_p, t_n, i_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDR port map (D => D, C => C, R => R, Q => q_p);
  off_n : FDS port map (D => D_n, C => C, S => R, Q => q_n);
  tri_p : FDS port map (D => T, C => C, S => R, Q => t_p);
  tri_n : FDS port map (D => T, C => C, S => R, Q => t_n);
  iff_p : FDR port map (D => i_p, C => C, R => R, Q => Q);
  pad_p : IOBUF_LVDS port map (I => q_p, T => t_p, O => i_p, IO => IO);
  pad_n : IOBUF_LVDS port map (I => q_n, T => t_n, O => dummy_o, IO => IOB);
end lvds_buff0; -- IOBUFDS_FDR_LVDS

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity IOBUFDS_FDRE_LVDS is
  port (
    D, T, CE, C, R : in std_logic;
    Q : out std_logic;
    IO, IOB : inout std_logic
  );
end entity IOBUFDS_FDRE_LVDS;

architecture lvds_buff0 of IOBUFDS_FDRE_LVDS is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute off_p IOB "true" -type string
-- set_attribute off_n IOB "true" -type string
-- set_attribute tri_p IOB "true" -type string
-- set_attribute tri_n IOB "true" -type string
-- set_attribute iff_p IOB "true" -type string
-- synopsys dc_script_end
  signal dummy_o, D_n, q_n, q_p, t_p, t_n, i_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDRE port map (D => D, CE => CE, C => C, R => R, Q => q_p);
  off_n : FDSE port map (D => D_n, CE => CE, C => C, S => R, Q => q_n);
  tri_p : FDSE port map (D => T, CE => CE, C => C, S => R, Q => t_p);
  tri_n : FDSE port map (D => T, CE => CE, C => C, S => R, Q => t_n);
  iff_p : FDRE port map (D => i_p, CE => CE, C => C, R => R, Q => Q);
  pad_p : IOBUF_LVDS port map (I => q_p, T => t_p, O => i_p, IO => IO);
  pad_n : IOBUF_LVDS port map (I => q_n, T => t_n, O => dummy_o, IO => IOB);
end lvds_buff0; -- IOBUFDS_FDRE_LVDS

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity IOBUFDS_FDS_LVDS is
  port (
    D, T, C, S : in std_logic;
    Q : out std_logic;
    IO, IOB : inout std_logic
  );
end entity IOBUFDS_FDS_LVDS;

architecture lvds_buff0 of IOBUFDS_FDS_LVDS is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute off_p IOB "true" -type string
-- set_attribute off_n IOB "true" -type string
-- set_attribute tri_p IOB "true" -type string
-- set_attribute tri_n IOB "true" -type string
-- set_attribute iff_p IOB "true" -type string
-- synopsys dc_script_end
  signal dummy_o, D_n, q_n, q_p, t_p, t_n, i_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDS port map (D => D, C => C, S => S, Q => q_p);
  off_n : FDR port map (D => D_n, C => C, R => S, Q => q_n);
  tri_p : FDS port map (D => T, C => C, S => S, Q => t_p);
  tri_n : FDS port map (D => T, C => C, S => S, Q => t_n);
  iff_p : FDS port map (D => i_p, C => C, S => S, Q => Q);
  pad_p : IOBUF_LVDS port map (I => q_p, T => t_p, O => i_p, IO => IO);
  pad_n : IOBUF_LVDS port map (I => q_n, T => t_n, O => dummy_o, IO => IOB);
end lvds_buff0; -- IOBUFDS_FDS_LVDS

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity IOBUFDS_FDSE_LVDS is
  port (
    D, T, CE, C, S : in std_logic;
    Q : out std_logic;
    IO, IOB : inout std_logic
  );
end entity IOBUFDS_FDSE_LVDS;

architecture lvds_buff0 of IOBUFDS_FDSE_LVDS is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute off_p IOB "true" -type string
-- set_attribute off_n IOB "true" -type string
-- set_attribute tri_p IOB "true" -type string
-- set_attribute tri_n IOB "true" -type string
-- set_attribute iff_p IOB "true" -type string
-- synopsys dc_script_end
  signal dummy_o, D_n, q_n, q_p, t_p, t_n, i_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  off_p : FDSE port map (D => D, CE => CE, C => C, S => S, Q => q_p);
  off_n : FDRE port map (D => D_n, CE => CE, C => C, R => S, Q => q_n);
  tri_p : FDSE port map (D => T, CE => CE, C => C, S => S, Q => t_p);
  tri_n : FDSE port map (D => T, CE => CE, C => C, S => S, Q => t_n);
  iff_p : FDSE port map (D => i_p, CE => CE, C => C, S => S, Q => Q);
  pad_p : IOBUF_LVDS port map (I => q_p, T => t_p, O => i_p, IO => IO);
  pad_n : IOBUF_LVDS port map (I => q_n, T => t_n, O => dummy_o, IO => IOB);
end lvds_buff0; -- IOBUFDS_FDSE_LVDS

-- ***************
-- IO Buffer Latch
-- ***************

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity IOBUFDS_LD_LVDS is
  port (
    D, T, G : in std_logic;
    Q : out std_logic;
    IO, IOB : inout std_logic
  );
end entity IOBUFDS_LD_LVDS;

architecture lvds_buff0 of IOBUFDS_LD_LVDS is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute olatch_p IOB "true" -type string
-- set_attribute olatch_n IOB "true" -type string
-- set_attribute tri_p IOB "true" -type string
-- set_attribute tri_n IOB "true" -type string
-- set_attribute ilatch_p IOB "true" -type string
-- synopsys dc_script_end
  signal dummy_o, D_n, q_n, q_p, t_p, t_n, i_p, CLR : std_logic;
begin
  CLR <= '0';
  inv_n : INV port map (I => D, O => D_n);
  olatch_p : LDC port map (D => D, G => G, CLR => CLR, Q => q_p);
  olatch_n : LDP port map (D => D_n, G => G, PRE => CLR, Q => q_n);
  tri_p : LDP port map (D => T, G => G, PRE => CLR, Q => t_p);
  tri_n : LDP port map (D => T, G => G, PRE => CLR, Q => t_n);
  ilatch_p : LD port map (D => i_p, G => G, Q => Q);
  pad_p : IOBUF_LVDS port map (I => q_p, T => t_p, O => i_p, IO => IO);
  pad_n : IOBUF_LVDS port map (I => q_n, T => t_n, O => dummy_o, IO => IOB);
end lvds_buff0; -- IOBUFDS_LD_LVDS

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity IOBUFDS_LDE_LVDS is
  port (
    D, T, GE, G : in std_logic;
    Q : out std_logic;
    IO, IOB : inout std_logic
  );
end entity IOBUFDS_LDE_LVDS;

architecture lvds_buff0 of IOBUFDS_LDE_LVDS is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute olatch_p IOB "true" -type string
-- set_attribute olatch_n IOB "true" -type string
-- set_attribute tri_p IOB "true" -type string
-- set_attribute tri_n IOB "true" -type string
-- set_attribute ilatch_p IOB "true" -type string
-- synopsys dc_script_end
  signal dummy_o, D_n, q_n, q_p, t_p, t_n, i_p, CLR : std_logic;
begin
  CLR <= '0';
  inv_n : INV port map (I => D, O => D_n);
  olatch_p : LDCE port map (D => D, GE => GE, G => G, CLR => CLR, Q => q_p);
  olatch_n : LDPE port map (D => D_n, GE => GE, G => G, PRE => CLR, Q => q_n);
  tri_p : LDPE port map (D => T, GE => GE, G => G, PRE => CLR, Q => t_p);
  tri_n : LDPE port map (D => T, GE => GE, G => G, PRE => CLR, Q => t_n);
  ilatch_p : LDE port map (D => i_p, GE => GE, G => G, Q => Q);
  pad_p : IOBUF_LVDS port map (I => q_p, T => t_p, O => i_p, IO => IO);
  pad_n : IOBUF_LVDS port map (I => q_n, T => t_n, O => dummy_o, IO => IOB);
end lvds_buff0; -- IOBUFDS_LDE_LVDS

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity IOBUFDS_LDC_LVDS is
  port (
    D, T, G, CLR : in std_logic;
    Q : out std_logic;
    IO, IOB : inout std_logic
  );
end entity IOBUFDS_LDC_LVDS;

architecture lvds_buff0 of IOBUFDS_LDC_LVDS is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute olatch_p IOB "true" -type string
-- set_attribute olatch_n IOB "true" -type string
-- set_attribute tri_p IOB "true" -type string
-- set_attribute tri_n IOB "true" -type string
-- set_attribute ilatch_p IOB "true" -type string
-- synopsys dc_script_end
  signal dummy_o, D_n, q_n, q_p, t_p, t_n, i_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  olatch_p : LDC port map (D => D, G => G, CLR => CLR, Q => q_p);
  olatch_n : LDP port map (D => D_n, G => G, PRE => CLR, Q => q_n);
  tri_p : LDP port map (D => T, G => G, PRE => CLR, Q => t_p);
  tri_n : LDP port map (D => T, G => G, PRE => CLR, Q => t_n);
  ilatch_p : LDC port map (D => i_p, G => G, CLR => CLR, Q => Q);
  pad_p : IOBUF_LVDS port map (I => q_p, T => t_p, O => i_p, IO => IO);
  pad_n : IOBUF_LVDS port map (I => q_n, T => t_n, O => dummy_o, IO => IOB);
end lvds_buff0; -- IOBUFDS_LDC_LVDS

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity IOBUFDS_LDCE_LVDS is
  port (
    D, T, GE, G, CLR : in std_logic;
    Q : out std_logic;
    IO, IOB : inout std_logic
  );
end entity IOBUFDS_LDCE_LVDS;

architecture lvds_buff0 of IOBUFDS_LDCE_LVDS is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute olatch_p IOB "true" -type string
-- set_attribute olatch_n IOB "true" -type string
-- set_attribute tri_p IOB "true" -type string
-- set_attribute tri_n IOB "true" -type string
-- set_attribute ilatch_p IOB "true" -type string
-- synopsys dc_script_end
  signal dummy_o, D_n, q_n, q_p, t_p, t_n, i_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  olatch_p : LDCE port map (D => D, GE => GE, G => G, CLR => CLR, Q => q_p);
  olatch_n : LDPE port map (D => D_n, GE => GE, G => G, PRE => CLR, Q => q_n);
  tri_p : LDPE port map (D => T, GE => GE, G => G, PRE => CLR, Q => t_p);
  tri_n : LDPE port map (D => T, GE => GE, G => G, PRE => CLR, Q => t_n);
  ilatch_p : LDCE port map (D => i_p, GE => GE, G => G, CLR => CLR, Q => Q);
  pad_p : IOBUF_LVDS port map (I => q_p, T => t_p, O => i_p, IO => IO);
  pad_n : IOBUF_LVDS port map (I => q_n, T => t_n, O => dummy_o, IO => IOB);
end lvds_buff0; -- IOBUFDS_LDCE_LVDS

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity IOBUFDS_LDP_LVDS is
  port (
    D, T, G, PRE : in std_logic;
    Q : out std_logic;
    IO, IOB : inout std_logic
  );
end entity IOBUFDS_LDP_LVDS;

architecture lvds_buff0 of IOBUFDS_LDP_LVDS is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute olatch_p IOB "true" -type string
-- set_attribute olatch_n IOB "true" -type string
-- set_attribute tri_p IOB "true" -type string
-- set_attribute tri_n IOB "true" -type string
-- set_attribute ilatch_p IOB "true" -type string
-- synopsys dc_script_end
  signal dummy_o, D_n, q_n, q_p, t_p, t_n, i_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  olatch_p : LDP port map (D => D, G => G, PRE => PRE, Q => q_p);
  olatch_n : LDC port map (D => D_n, G => G, CLR => PRE, Q => q_n);
  tri_p : LDP port map (D => T, G => G, PRE => PRE, Q => t_p);
  tri_n : LDP port map (D => T, G => G, PRE => PRE, Q => t_n);
  ilatch_p : LDP port map (D => i_p, G => G, PRE => PRE, Q => Q);
  pad_p : IOBUF_LVDS port map (I => q_p, T => t_p, O => i_p, IO => IO);
  pad_n : IOBUF_LVDS port map (I => q_n, T => t_n, O => dummy_o, IO => IOB);
end lvds_buff0; -- IOBUFDS_LDP_LVDS

library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity IOBUFDS_LDPE_LVDS is
  port (
    D, T, GE, G, PRE : in std_logic;
    Q : out std_logic;
    IO, IOB : inout std_logic
  );
end entity IOBUFDS_LDPE_LVDS;

architecture lvds_buff0 of IOBUFDS_LDPE_LVDS is
-- synopsys dc_script_begin
-- set_dont_touch find(cell,"*")
-- set_dont_touch current_design
-- set_attribute olatch_p IOB "true" -type string
-- set_attribute olatch_n IOB "true" -type string
-- set_attribute tri_p IOB "true" -type string
-- set_attribute tri_n IOB "true" -type string
-- set_attribute ilatch_p IOB "true" -type string
-- synopsys dc_script_end
  signal dummy_o, D_n, q_n, q_p, t_p, t_n, i_p : std_logic;
begin
  inv_n : INV port map (I => D, O => D_n);
  olatch_p : LDPE port map (D => D, GE => GE, G => G, PRE => PRE, Q => q_p);
  olatch_n : LDCE port map (D => D_n, GE => GE, G => G, CLR => PRE, Q => q_n);
  tri_p : LDPE port map (D => T, GE => GE, G => G, PRE => PRE, Q => t_p);
  tri_n : LDPE port map (D => T, GE => GE, G => G, PRE => PRE, Q => t_n);
  ilatch_p : LDPE port map (D => i_p, GE => GE, G => G, PRE => PRE, Q => Q);
  pad_p : IOBUF_LVDS port map (I => q_p, T => t_p, O => i_p, IO => IO);
  pad_n : IOBUF_LVDS port map (I => q_n, T => t_n, O => dummy_o, IO => IOB);
end lvds_buff0; -- IOBUFDS_LDPE_LVDS