15进制.txt

FPGA里面的计数器相关资料及程序汇总大全

library ieee;
use ieee.std-logic_1164.all;
entity counter is
port(clk:in std_logic;
input: in std_logic_vector(3 donto 0);
output: out std_logic_vector(3 downto )
);
end couter;
architecture rtl is
signal q:integer range 0 to 15;
begin
process(clk)
if clk'event and clk='1'
q<=q+1;
if q = 15 then--15计数器
q<=0;
end if;
end if;
end process;
process(q)
begin
if q=0 then
null;
else output<=input;
end if;
end process;
end rtl;