📄 vhdl 计数器源程序.mht
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<BR><BR>
<P><STRONG>=CA=AE=CE=E5=BC=C6=CA=FD=C6=F7</STRONG></P>
<P>library ieee;<BR>use ieee.std_logic_1164.all;<BR>use=20
ieee.std_logic_unsigned.all;<BR>ENTITY fiveteencout =
IS<BR>PORT(clk,reset,enable=20
: IN std_logic; count : OUT std_logic_vector(3 downto 0));<BR>END=20
fiveteencout;<BR>ARCHITECTURE counter OF fiveteencout IS<BR>SIGNAL=20
count_int:std_logic_vector(0 to=20
3);<BR>BEGIN<BR>PROCESS(clk,reset)<BR>BEGIN<BR>WAIT UNTIL=20
rising_edge(clk);<BR>IF reset =3D '1' THEN<BR>count_int <=3D (OTHERS =
=3D>=20
'0');<BR>ELSIF enable =3D '1' THEN<BR>IF(count_int=3D"1110")=20
THEN<BR>count_int<=3D"0000";</P>
<P>ELSE<BR>count_int <=3D count_int 1;<BR>--ELSE<BR>-- NULL ;<BR>--IF =
(count_int=3D"1001") THEN<BR>--count_int<=3D"0000";<BR>END IF;<BR>END =
IF;<BR>END=20
PROCESS;<BR>count <=3D count_int;<BR>-- IF (reset=3D'0')=20
then<BR>--q<=3D"0000";<BR>---ELSIF(clk'event and clk=3D'1') =
THEN<BR>--q<=3Dq=20
1;<BR>--IF (q<=3D"1001") then<BR>--q<=3D"0000";<BR>---END =
IF;<BR>--IF=20
(reset<=3D'1')THEN<BR>--q<=3D"00";<BR>--ELSIF<BR>--wait until =
(clk'event and=20
clk=3D'1');<BR>--WAIT UNTIL (clk'EVENT AND clk =3D '1');</P>
<P>--WAIT UNTIL (clock'EVENT AND clock =3D '1');<BR>-- q<=3Dq =
'1';<BR>--end=20
if;<BR>--count<=3Dq;<BR>-- WAIT UNTIL clock =3D '1';<BR>--if =
(clock'event and=20
clock=3D'1')then<BR>--WAIT UNTIL rising_edge(clock);<BR>--clock'event =
and=20
clock=3D'1';<BR>--count <=3D 0;<BR>--WAIT UNTIL (clock'EVENT AND =
clock =3D=20
'1');<BR>--WAIT riseedge clock =3D '1';<BR>--if (clock'event and =
clock=3D'1')=20
then<BR>--WAIT UNTIL rising_edge(clock);<BR>--count <=3D 1;<BR>--WAIT =
UNTIL=20
(clock'EVENT AND clock =3D '1');<BR>--WAIT UNTIL clock =3D '1';<BR>--if =
(clock'event=20
and clock=3D'1')then<BR>--WAIT UNTIL rising_edge(clock);<BR>--count =
<=3D=20
2;<BR>--end if;<BR>--end if;<BR>--end if;<BR>-- END PROCESS;<BR>END =
counter;</P>
<P><STRONG>=CA=AE=CB=C4=BC=C6=CA=FD=C6=F7</STRONG></P>
<P>library ieee;<BR>use ieee.std_logic_1164.all;<BR>use=20
ieee.std_logic_unsigned.all;<BR>ENTITY fourteencout =
IS<BR>PORT(clk,reset,enable=20
: IN std_logic; count : OUT std_logic_vector(3 downto 0));<BR>END=20
fourteencout;<BR>ARCHITECTURE counter OF fourteencout IS<BR>SIGNAL=20
count_int:std_logic_vector(0 to=20
3);<BR>BEGIN<BR>PROCESS(clk,reset)<BR>BEGIN<BR>WAIT UNTIL=20
rising_edge(clk);<BR>IF reset =3D '1' THEN<BR>count_int <=3D (OTHERS =
=3D>=20
'0');<BR>ELSIF enable =3D '1' THEN<BR>IF(count_int=3D"1101")=20
THEN<BR>count_int<=3D"0000";</P>
<P>ELSE<BR>count_int <=3D count_int 1;<BR>--ELSE<BR>-- NULL ;<BR>--IF =
(count_int=3D"1001") THEN<BR>--count_int<=3D"0000";<BR>END IF;<BR>END =
IF;<BR>END=20
PROCESS;<BR>count <=3D count_int;<BR>-- IF (reset=3D'0')=20
then<BR>--q<=3D"0000";<BR>---ELSIF(clk'event and clk=3D'1') =
THEN<BR>--q<=3Dq=20
1;<BR>--IF (q<=3D"1001") then<BR>--q<=3D"0000";<BR>---END =
IF;<BR>--IF=20
(reset<=3D'1')THEN<BR>--q<=3D"00";<BR>--ELSIF<BR>--wait until =
(clk'event and=20
clk=3D'1');<BR>--WAIT UNTIL (clk'EVENT AND clk =3D '1');</P>
<P>--WAIT UNTIL (clock'EVENT AND clock =3D '1');<BR>-- q<=3Dq =
'1';<BR>--end=20
if;<BR>--count<=3Dq;<BR>-- WAIT UNTIL clock =3D '1';<BR>--if =
(clock'event and=20
clock=3D'1')then<BR>--WAIT UNTIL rising_edge(clock);<BR>--clock'event =
and=20
clock=3D'1';<BR>--count <=3D 0;<BR>--WAIT UNTIL (clock'EVENT AND =
clock =3D=20
'1');<BR>--WAIT riseedge clock =3D '1';<BR>--if (clock'event and =
clock=3D'1')=20
then<BR>--WAIT UNTIL rising_edge(clock);<BR>--count <=3D 1;<BR>--WAIT =
UNTIL=20
(clock'EVENT AND clock =3D '1');<BR>--WAIT UNTIL clock =3D '1';<BR>--if =
(clock'event=20
and clock=3D'1')then<BR>--WAIT UNTIL rising_edge(clock);<BR>--count =
<=3D=20
2;<BR>--end if;<BR>--end if;<BR>--end if;<BR>-- END PROCESS;<BR>END =
counter;</P>
<P><STRONG>=CA=AE=C8=FD=BC=C6=CA=FD=C6=F7</STRONG></P>
<P>library ieee;<BR>use ieee.std_logic_1164.all;<BR>use=20
ieee.std_logic_unsigned.all;<BR>ENTITY thireteencout =
IS<BR>PORT(clk,reset,enable=20
: IN std_logic; count : OUT std_logic_vector(3 downto 0));<BR>END=20
thireteencout;<BR>ARCHITECTURE counter OF thireteencout IS<BR>SIGNAL=20
count_int:std_logic_vector(0 to=20
3);<BR>BEGIN<BR>PROCESS(clk,reset)<BR>BEGIN<BR>WAIT UNTIL=20
rising_edge(clk);<BR>IF reset =3D '1' THEN<BR>count_int <=3D (OTHERS =
=3D>=20
'0');<BR>ELSIF enable =3D '1' THEN<BR>IF(count_int=3D"1100")=20
THEN<BR>count_int<=3D"0000";</P>
<P>ELSE<BR>count_int <=3D count_int 1;<BR>--ELSE<BR>-- NULL ;<BR>--IF =
(count_int=3D"1001") THEN<BR>--count_int<=3D"0000";<BR>END IF;<BR>END =
IF;<BR>END=20
PROCESS;<BR>count <=3D count_int;<BR>-- IF (reset=3D'0')=20
then<BR>--q<=3D"0000";<BR>---ELSIF(clk'event and clk=3D'1') =
THEN<BR>--q<=3Dq=20
1;<BR>--IF (q<=3D"1001") then<BR>--q<=3D"0000";<BR>---END =
IF;<BR>--IF=20
(reset<=3D'1')THEN<BR>--q<=3D"00";<BR>--ELSIF<BR>--wait until =
(clk'event and=20
clk=3D'1');<BR>--WAIT UNTIL (clk'EVENT AND clk =3D '1');</P>
<P>--WAIT UNTIL (clock'EVENT AND clock =3D '1');<BR>-- q<=3Dq =
'1';<BR>--end=20
if;<BR>--count<=3Dq;<BR>-- WAIT UNTIL clock =3D '1';<BR>--if =
(clock'event and=20
clock=3D'1')then<BR>--WAIT UNTIL rising_edge(clock);<BR>--clock'event =
and=20
clock=3D'1';<BR>--count <=3D 0;<BR>--WAIT UNTIL (clock'EVENT AND =
clock =3D=20
'1');<BR>--WAIT riseedge clock =3D '1';<BR>--if (clock'event and =
clock=3D'1')=20
then<BR>--WAIT UNTIL rising_edge(clock);<BR>--count <=3D 1;<BR>--WAIT =
UNTIL=20
(clock'EVENT AND clock =3D '1');<BR>--WAIT UNTIL clock =3D '1';<BR>--if =
(clock'event=20
and clock=3D'1')then<BR>--WAIT UNTIL rising_edge(clock);<BR>--count =
<=3D=20
2;<BR>--end if;<BR>--end if;<BR>--end if;<BR>-- END PROCESS;<BR>END =
counter;</P>
<P><STRONG>=CA=AE=B6=FE=BC=C6=CA=FD=C6=F7</STRONG></P>
<P>library ieee;<BR>use ieee.std_logic_1164.all;<BR>use=20
ieee.std_logic_unsigned.all;<BR>ENTITY twelvecout =
IS<BR>PORT(clk,reset,enable :=20
IN std_logic; count : OUT std_logic_vector(3 downto 0));<BR>END=20
twelvecout;<BR>ARCHITECTURE counter OF twelvecout IS<BR>SIGNAL=20
count_int:std_logic_vector(0 to=20
3);<BR>BEGIN<BR>PROCESS(clk,reset)<BR>BEGIN<BR>WAIT UNTIL=20
rising_edge(clk);<BR>IF reset =3D '1' THEN<BR>count_int <=3D (OTHERS =
=3D>=20
'0');<BR>ELSIF enable =3D '1' THEN<BR>IF(count_int=3D"1011")=20
THEN<BR>count_int<=3D"0000";</P>
<P>ELSE<BR>count_int <=3D count_int 1;<BR>--ELSE<BR>-- NULL ;<BR>--IF =
(count_int=3D"1001") THEN<BR>--count_int<=3D"0000";<BR>END IF;<BR>END =
IF;<BR>END=20
PROCESS;<BR>count <=3D count_int;<BR>-- IF (reset=3D'0')=20
then<BR>--q<=3D"0000";<BR>---ELSIF(clk'event and clk=3D'1') =
THEN<BR>--q<=3Dq=20
1;<BR>--IF (q<=3D"1001") then<BR>--q<=3D"0000";<BR>---END =
IF;<BR>--IF=20
(reset<=3D'1')THEN<BR>--q<=3D"00";<BR>--ELSIF<BR>--wait until =
(clk'event and=20
clk=3D'1');<BR>--WAIT UNTIL (clk'EVENT AND clk =3D '1');</P>
<P>--WAIT UNTIL (clock'EVENT AND clock =3D '1');<BR>-- q<=3Dq =
'1';<BR>--end=20
if;<BR>--count<=3Dq;<BR>-- WAIT UNTIL clock =3D '1';<BR>--if =
(clock'event and=20
clock=3D'1')then<BR>--WAIT UNTIL rising_edge(clock);<BR>--clock'event =
and=20
clock=3D'1';<BR>--count <=3D 0;<BR>--WAIT UNTIL (clock'EVENT AND =
clock =3D=20
'1');<BR>--WAIT riseedge clock =3D '1';<BR>--if (clock'event and =
clock=3D'1')=20
then<BR>--WAIT UNTIL rising_edge(clock);<BR>--count <=3D 1;<BR>--WAIT =
UNTIL=20
(clock'EVENT AND clock =3D '1');<BR>--WAIT UNTIL clock =3D '1';<BR>--if =
(clock'event=20
and clock=3D'1')then<BR>--WAIT UNTIL rising_edge(clock);<BR>--count =
<=3D=20
2;<BR>--end if;<BR>--end if;<BR>--end if;<BR>-- END PROCESS;<BR>END =
counter;</P>
<P><STRONG>=CA=AE=D2=BB=BC=C6=CA=FD=C6=F7</STRONG></P>
<P>library ieee;<BR>use ieee.std_logic_1164.all;<BR>use=20
ieee.std_logic_unsigned.all;<BR>ENTITY elevencout =
IS<BR>PORT(clk,reset,enable :=20
IN std_logic; count : OUT std_logic_vector(3 downto 0));<BR>END=20
elevencout;<BR>ARCHITECTURE counter OF elevencout IS<BR>SIGNAL=20
count_int:std_logic_vector(0 to=20
3);<BR>BEGIN<BR>PROCESS(clk,reset)<BR>BEGIN<BR>WAIT UNTIL=20
rising_edge(clk);<BR>IF reset =3D '1' THEN<BR>count_int <=3D (OTHERS =
=3D>=20
'0');<BR>ELSIF enable =3D '1' THEN<BR>IF(count_int=3D"1010")=20
THEN<BR>count_int<=3D"0000";</P>
<P>ELSE<BR>count_int <=3D count_int 1;<BR>--ELSE<BR>-- NULL ;<BR>--IF =
(count_int=3D"1001") THEN<BR>--count_int<=3D"0000";<BR>END IF;<BR>END =
IF;<BR>END=20
PROCESS;<BR>count <=3D count_int;<BR>-- IF (reset=3D'0')=20
then<BR>--q<=3D"0000";<BR>---ELSIF(clk'event and clk=3D'1') =
THEN<BR>--q<=3Dq=20
1;<BR>--IF (q<=3D"1001") then<BR>--q<=3D"0000";<BR>---END =
IF;<BR>--IF=20
(reset<=3D'1')THEN<BR>--q<=3D"00";<BR>--ELSIF<BR>--wait until =
(clk'event and=20
clk=3D'1');<BR>--WAIT UNTIL (clk'EVENT AND clk =3D '1');</P>
<P>--WAIT UNTIL (clock'EVENT AND clock =3D '1');<BR>-- q<=3Dq =
'1';<BR>--end=20
if;<BR>--count<=3Dq;<BR>-- WAIT UNTIL clock =3D '1';<BR>--if =
(clock'event and=20
clock=3D'1')then<BR>--WAIT UNTIL rising_edge(clock);<BR>--clock'event =
and=20
clock=3D'1';<BR>--count <=3D 0;<BR>--WAIT UNTIL (clock'EVENT AND =
clock =3D=20
'1');<BR>--WAIT riseedge clock =3D '1';<BR>--if (clock'event and =
clock=3D'1')=20
then<BR>--WAIT UNTIL rising_edge(clock);<BR>--count <=3D 1;<BR>--WAIT =
UNTIL=20
(clock'EVENT AND clock =3D '1');<BR>--WAIT UNTIL clock =3D '1';<BR>--if =
(clock'event=20
and clock=3D'1')then<BR>--WAIT UNTIL rising_edge(clock);<BR>--count =
<=3D=20
2;<BR>--end if;<BR>--end if;<BR>--end if;<BR>-- END PROCESS;<BR>END =
counter;</P>
<P> </P>
<P><STRONG>=CA=AE=BC=C6=CA=FD=C6=F7</STRONG></P>
<P>library ieee;<BR>use ieee.std_logic_1164.all;<BR>use=20
ieee.std_logic_unsigned.all;<BR>ENTITY count IS<BR>PORT(clk,reset,enable =
: IN=20
std_logic; count : OUT std_logic_vector(3 downto 0));<BR>END=20
count;<BR>ARCHITECTURE counter OF count IS<BR>SIGNAL=20
count_int:std_logic_vector(0 to=20
3);<BR>BEGIN<BR>PROCESS(clk,reset)<BR>BEGIN<BR>WAIT UNTIL=20
rising_edge(clk);<BR>IF reset =3D '1' THEN<BR>count_int <=3D (OTHERS =
=3D>=20
'0');<BR>ELSIF enable =3D '1' THEN<BR>IF(count_int=3D"1001")=20
THEN<BR>count_int<=3D"0000";</P>
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