📄 计数器——vhdl源码【原】_莱密之家[金鼎国]—电子爱好者—博客—湖北武汉—中南民族大学.mht
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ieee.std_logic_unsigned.all;<BR><BR>entity cout10=20
is<BR>port(<BR> clk_in,rest_in:in=20
std_logic;<BR> clk_key_in:in=20
std_logic;--=B0=B4=BC=FC<BR> clk_md_in:in =
std_logic_vector(2=20
downto 0);--=BC=D3=C4=A3=CA=BD=CE=BB--000 =BC=D31 --001 =BC=D310 =
010 =BC=D3100 011=20
=BC=D31000<BR> bt_out:out std_logic_vector(3 =
downto=20
0);--=CA=FD=C2=EB=B9=DC=CE=BB=D1=A1<BR> cout:out =
std_logic_vector(6 downto=20
0)<BR> );<BR>end;<BR><BR>architecture lammy02 of =
cout10=20
is<BR> component showled<BR> =20
port(<BR> =20
indata:in std_logic_vector(3 downto=20
0);<BR> =20
outdata:out std_logic_vector(6 downto 0)<BR> =20
);<BR> end =
component showled;<BR> component cnt10=20
<BR> =
port(<BR> =20
rest,clk:in=20
std_logic;<BR> =
=20
clk_key:in std_logic;--=B0=B4=BC=FC<BR> =
=20
clk_md:in std_logic_vector(2 downto =
0);--=BC=D3=C4=A3=CA=BD=CE=BB--000 =BC=D31=20
--001 =BC=D310 010 =BC=D3100 011 =BC=D31000<BR> =
=20
bt:out std_logic_vector(3 downto=20
0);--=CA=FD=C2=EB=B9=DC=CE=BB=D1=A1<BR> =
=20
cout1:out std_logic_vector(3 downto =
0)--=B8=F6=CE=BB<BR> =20
);<BR> end component=20
cnt10;<BR> =
signal=20
d_cout1:std_logic_vector(3 downto 0);<BR> =20
begin<BR> u1: cnt10 port map=20
=
(clk=3D>clk_in,rest=3D>rest_in,clk_key=3D>clk_key_in,clk_md=3D&g=
t;clk_md_in,bt=3D>bt_out,cout1=3D>d_cout1);<BR> =20
u2: showled port map=20
=
(indata=3D>d_cout1,outdata=3D>cout);<BR>end;<BR><BR><BR>///////////=
//////////showled.vhd<BR>library=20
ieee;<BR>use ieee.std_logic_1164.all;<BR>use=20
ieee.std_logic_unsigned.all;<BR><BR>entity showled=20
is<BR>port(<BR> indata:in std_logic_vector(3 =
downto=20
0);<BR> outdata:out std_logic_vector(6 downto=20
0)<BR> );<BR>end;<BR><BR>architecture lammy01 of =
showled=20
is<BR>--signal in_data:std_logic_vector(3 downto=20
0);<BR>begin<BR> =
process(indata)<BR> =20
begin<BR> case indata=20
is<BR> when "0000" =3D>=20
outdata<=3D"0111111";--0<BR> =
when=20
"0001" =3D> outdata<=3D"0000110";--1<BR> =20
when "0010" =3D>=20
outdata<=3D"1011011";--2<BR> =
when=20
"0011" =3D> outdata<=3D"1001111";--3<BR> =20
when "0100" =3D>=20
outdata<=3D"1100110";--4<BR> =
when=20
"0101" =3D> outdata<=3D"1101101";--5<BR> =20
when "0110" =3D>=20
outdata<=3D"1111101";--6<BR> =
when=20
"0111" =3D> outdata<=3D"0000111";--7<BR> =20
when "1000" =3D>=20
outdata<=3D"1111111";--8<BR> =
when=20
"1001" =3D> outdata<=3D"1101111";--9<BR> =20
when others =3D> null;<BR> =
end case;<BR> end=20
process;<BR>end;<BR><BR><BR>///////////////cnt10.vhd<BR>library=20
ieee;<BR>use ieee.std_logic_1164.all;<BR>use=20
ieee.std_logic_unsigned.all;<BR><BR>entity cnt10=20
is<BR>port(<BR> rest,clk:in=20
std_logic;<BR> clk_key:in=20
std_logic;--=B0=B4=BC=FC<BR> clk_md:in =
std_logic_vector(2 downto=20
0);--=BC=D3=C4=A3=CA=BD=CE=BB--000 =BC=D31 --001 =BC=D310 010 =
=BC=D3100 011 =BC=D31000<BR><BR> =20
bt:out std_logic_vector(3 downto =
0);--=CA=FD=C2=EB=B9=DC=CE=BB=D1=A1<BR> =20
cout1:out std_logic_vector(3 downto =
0)--=B8=F6=CE=BB<BR> =20
);<BR>end;<BR><BR>architecture lammy02 of cnt10 =
is<BR> =20
type state is(s0,s1,s2,s3);<BR> signal=20
led_state:state;<BR> signal=20
outdata_1,outdata_2,outdata_3,outdata_4:std_logic_vector(3 downto=20
=
0):=3D"0000";<BR>begin<BR><BR>lammy_01:process(rest,clk,led_state)<BR>&nb=
sp; =20
begin<BR> if rest=3D'1' then=20
cout1<=3D"0000";led_state<=3Ds0;<BR> =20
elsif clk'event and clk=3D'1' then =
<BR> =20
case led_state is<BR> =20
when s0 =3D>=20
=
bt<=3D"1000";cout1<=3Doutdata_1;led_state<=3Ds1;<BR> =
=20
when s1 =3D>=20
=
bt<=3D"0100";cout1<=3Doutdata_2;led_state<=3Ds2;<BR> =
=20
when s2 =3D>=20
=
bt<=3D"0010";cout1<=3Doutdata_3;led_state<=3Ds3;<BR> =
=20
when s3 =3D>=20
=
bt<=3D"0001";cout1<=3Doutdata_4;led_state<=3Ds0;<BR> =
=20
end case;<BR> =
end=20
if;<BR> end=20
process;<BR>lammy_02:process(clk_key)<BR> =
variable=20
cout_1,cout_2,cout_3,cout_4:std_logic_vector(3 downto=20
0);<BR> begin<BR> =
=20
if rising_edge(clk_key) then <BR> =
=20
if clk_md=3D"000" then<BR> =20
if =
cout_1=3D"1001"=20
and cout_2=3D"1001" and cout_3=3D"1001" and cout_4=3D"1001"=20
<BR> =20
then cout_1:=3D"1001" ; =
cout_2:=3D"1001"=20
; cout_3:=3D"1001" ; cout_4:=3D"1001";<BR> =20
=20
elsif cout_1=3D"1001" and cout_2=3D"1001" and =
cout_3=3D"1001"=20
then=20
=
cout_4:=3Dcout_4+1;cout_1:=3D"0000";cout_2:=3D"0000";cout_3:=3D"0000";<BR=
> =20
=20
elsif cout_1=3D"1001" and=20
cout_2=3D"1001" then=20
=
cout_3:=3Dcout_3+1;cout_1:=3D"0000";cout_2:=3D"0000";<BR> &nbs=
p;=20
=20
elsif=20
cout_1=3D"1001" then =
cout_2:=3Dcout_2+1;cout_1:=3D"0000";<BR> =20
=20
=20
else cout_1:=3Dcout_1+1;<BR> =20
end=20
if;<BR> =
elsif=20
clk_md=3D"001" then <BR> =20
if cout_2=3D"1001" and =
cout_3=3D"1001"=20
and cout_4=3D"1001" <BR> =20
then=20
cout_2:=3D"1001" ; cout_3:=3D"1001" ; =
cout_4:=3D"1001";<BR> =20
=20
elsif cout_2=3D"1001" and cout_3=3D"1001" then=20
=
cout_4:=3Dcout_4+1;cout_2:=3D"0000";cout_3:=3D"0000";<BR> &nbs=
p;=20
=20
elsif cout_2=3D"1001" then=20
cout_3:=3Dcout_3+1; cout_2:=3D"0000";<BR> =
=20
=20
else cout_2:=3Dcout_2+1;<BR> =20
end=20
if;<BR> =
elsif=20
clk_md=3D"010" then<BR> =20
if cout_3=3D"1001" and =
cout_4=3D"1001"=20
<BR> =20
then cout_3:=3D"1001" ;=20
cout_4:=3D"1001";<BR> =20
elsif=20
cout_3=3D"1001" then =
cout_4:=3Dcout_4+1;cout_3:=3D"0000";<BR> =20
=20
else cout_3:=3Dcout_3+1;<BR> =20
end=20
if;<BR> =
elsif=20
clk_md=3D"011" then<BR> =20
if cout_4=3D"1001" then=20
cout_4:=3D"1001";<BR> =20
else=20
cout_4:=3Dcout_4+1;<BR> =20
end =
if;<BR> =20
end =
if;<BR> =20
end if;<BR> =
=20
outdata_1<=3Dcout_1;<BR> =20
outdata_2<=3Dcout_2;<BR> =20
outdata_3<=3Dcout_3;<BR> =20
outdata_4<=3Dcout_4;<BR> end=20
process;<BR>end;</DIV></TD></TR></TBODY></TABLE><BR>
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