ffd.v

来自「一个实现简单的数字锁相环Verilog代码」· Verilog 代码 · 共 21 行

module FFD(clock,
           reset,
           D,
			  Q,Q_not
			  );
input  clock,
       reset,
       D;
output Q,Q_not;

reg Q;

always @(posedge clock or negedge reset)
if(~reset)
   Q <= 0;
else
   Q <= D;

assign Q_not = ~Q;

endmodule