k_counter.v

来自「一个实现简单的数字锁相环Verilog代码」· Verilog 代码 · 共 62 行

module k_counter(Kclock,
                 reset,
                 dnup,enable,
                 Kmode,
                 carry,
                 borrow
                  );
input  Kclock,
       reset,
       dnup,
       enable;
input[2:0]  Kmode;
output carry,
       borrow;

reg[8:0]   count; /*可逆计数器*/
reg[8:0]   Ktop;  /*预设模值寄存器*/

/*根据计数器模值设置信号Kmode来设置预设模值寄存器的值*/
always @(Kmode)
begin
case(Kmode)
   3'b001:  Ktop = 7;
   3'b010:  Ktop = 15;
   3'b011:  Ktop = 31;
   3'b100:  Ktop = 63;
   3'b101:  Ktop = 127;
   3'b110:  Ktop = 255;
   3'b111:  Ktop = 511;
   default:Ktop = 15;
endcase
end

/*根据鉴相器输出的加减控制信号dnup进行可逆计数器的加减运算*/
always @(posedge Kclock or negedge reset)
begin
   if(~reset)
      count <= 0;
   else if(enable)
   begin
      if(~dnup)    // 进行加运算
      begin
         if(count==Ktop)
            count <= 0;
         else
            count <= count+1;
      end
      else begin   // 进行减运算
         if(count==0)
            count <= Ktop;
         else
            count <= count-1;
      end
   end
end

assign carry = enable&(~dnup)&(count==Ktop);
assign borrow = enable&(dnup)&(count==0);

endmodule