dpll_tb.v

来自「一个实现简单的数字锁相环Verilog代码」· Verilog 代码 · 共 30 行

module dpll_tb;
reg   clock,
		  reset,
       enable,
       Fin;
reg[2:0]  Kmode;
wire   Fout;

DPLL DPLL(.sys_clock(clock),
          .reset(reset),
          .enable(enable),
          .Fin(Fin),
          .Fout(Fout),
          .Kmode(Kmode)
          );

initial	begin
    clock = 0;
    enable = 1;
    Fin = 0;
    Kmode = 3'b110;
    reset = 1;
    #46  reset = 0;
    #70 reset = 1; 
end

always #10 clock = ~clock;   // sys_clock
always #5120 Fin = ~Fin;			// Fo

endmodule