dpll.v.bak

一个实现简单的数字锁相环Verilog代码

module DPLL(sys_clock,
             reset,
             enable,
             Fin,
             Fout,
             Kmode
             );
input  sys_clock,
       reset,
       enable,
       Fin;
input[2:0] Kmode;
output Fout;

wire se,
     carry,borrow,
     IDclock,
     IDout;
reg[2:0]	cnt_H;    // H =8
reg[5:0]	cnt_N;    // N =32

/***********  Phrase Detector   ***********/     
xor cmp(se, Fin, Fout);

/***********  DLF   ***********/  
k_counter k_counter(.Kclock(sys_clock),
                    .reset(reset),
                    .dnup(se),
                    .enable(enable),
                    .Kmode(Kmode),
                    .carry(carry),
                    .borrow(borrow)
                     );

reg	q1,q2,
		carry_out;
wire	clr = carry_out;
always @(posedge carry or negedge reset)
if(~reset)
	q1 <= 0;
else
	q1 <= 1;
always @(posedge IDclock or negedge reset)
if(~reset)
	q2 <= 0;
else	
	q2 <= q1;
always @(posedge IDclock or negedge reset)	
if(~reset|clr)
	carry_out <= 0;
else
	carry_out <= q2;

reg	q3,q4,
		borrow_out;
wire	clr2 = (~borrow)|borrow_out;
always @(posedge borrow or negedge clr2)
	if(clr)
		q3 <= 0;
	else
		q3 <= 1;
always @(posedge IDclock)
	q4 <= q3;
always @(posedge IDclock)	
	borrow_out <= q4;	
			
always @(posedge sys_clock or negedge reset)		// Genarate IDclock from sys_clock
if(~reset)
	cnt_H <= 0;
else
	cnt_H <= cnt_H+1;
assign	IDclock = cnt_H[2];		

/***********  DCO   ***********/                       
id_counter id_counter(.IDclock(IDclock),
                      .reset(reset),
                      .inc(carry_out),
                      .dec(borrow_out),
                      .IDout(IDout)
                      );

always @(posedge 	IDclock or negedge reset)		// Genarate Fout from IDout
if(~reset)
	cnt_N <= 0;
else
	cnt_N <= cnt_N+1;
assign	Fout = cnt_N[3];	




endmodule