speaker.tan.qmsg

verilog语言写的杨声器!

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register counter\[4\] register speaker~reg0 195.77 MHz 5.108 ns Internal " "Info: Clock \"clk\" has Internal fmax of 195.77 MHz between source register \"counter\[4\]\" and destination register \"speaker~reg0\" (period= 5.108 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.847 ns + Longest register register " "Info: + Longest register to register delay is 4.847 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter\[4\] 1 REG LC_X33_Y14_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X33_Y14_N5; Fanout = 4; REG Node = 'counter\[4\]'" {  } { { "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" "" { Report "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/FPGAtest/speaker/db/speaker.quartus_db" { Floorplan "D:/FPGAtest/speaker/" "" "" { counter[4] } "NODE_NAME" } "" } } { "speaker.v" "" { Text "D:/FPGAtest/speaker/speaker.v" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.167 ns) + CELL(0.590 ns) 1.757 ns reduce_nor~101 2 COMB LC_X33_Y13_N1 1 " "Info: 2: + IC(1.167 ns) + CELL(0.590 ns) = 1.757 ns; Loc. = LC_X33_Y13_N1; Fanout = 1; COMB Node = 'reduce_nor~101'" {  } { { "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" "" { Report "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/FPGAtest/speaker/db/speaker.quartus_db" { Floorplan "D:/FPGAtest/speaker/" "" "1.757 ns" { counter[4] reduce_nor~101 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.437 ns) + CELL(0.590 ns) 2.784 ns reduce_nor~103 3 COMB LC_X33_Y13_N8 15 " "Info: 3: + IC(0.437 ns) + CELL(0.590 ns) = 2.784 ns; Loc. = LC_X33_Y13_N8; Fanout = 15; COMB Node = 'reduce_nor~103'" {  } { { "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" "" { Report "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/FPGAtest/speaker/db/speaker.quartus_db" { Floorplan "D:/FPGAtest/speaker/" "" "1.027 ns" { reduce_nor~101 reduce_nor~103 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.196 ns) + CELL(0.867 ns) 4.847 ns speaker~reg0 4 REG LC_X31_Y13_N3 2 " "Info: 4: + IC(1.196 ns) + CELL(0.867 ns) = 4.847 ns; Loc. = LC_X31_Y13_N3; Fanout = 2; REG Node = 'speaker~reg0'" {  } { { "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" "" { Report "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/FPGAtest/speaker/db/speaker.quartus_db" { Floorplan "D:/FPGAtest/speaker/" "" "2.063 ns" { reduce_nor~103 speaker~reg0 } "NODE_NAME" } "" } } { "speaker.v" "" { Text "D:/FPGAtest/speaker/speaker.v" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.047 ns 42.23 % " "Info: Total cell delay = 2.047 ns ( 42.23 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns 57.77 % " "Info: Total interconnect delay = 2.800 ns ( 57.77 % )" {  } {  } 0}  } { { "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" "" { Report "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/FPGAtest/speaker/db/speaker.quartus_db" { Floorplan "D:/FPGAtest/speaker/" "" "4.847 ns" { counter[4] reduce_nor~101 reduce_nor~103 speaker~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "4.847 ns" { counter[4] reduce_nor~101 reduce_nor~103 speaker~reg0 } { 0.000ns 1.167ns 0.437ns 1.196ns } { 0.000ns 0.590ns 0.590ns 0.867ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.962 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 44 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 44; CLK Node = 'clk'" {  } { { "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" "" { Report "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/FPGAtest/speaker/db/speaker.quartus_db" { Floorplan "D:/FPGAtest/speaker/" "" "" { clk } "NODE_NAME" } "" } } { "speaker.v" "" { Text "D:/FPGAtest/speaker/speaker.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns speaker~reg0 2 REG LC_X31_Y13_N3 2 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X31_Y13_N3; Fanout = 2; REG Node = 'speaker~reg0'" {  } { { "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" "" { Report "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/FPGAtest/speaker/db/speaker.quartus_db" { Floorplan "D:/FPGAtest/speaker/" "" "1.493 ns" { clk speaker~reg0 } "NODE_NAME" } "" } } { "speaker.v" "" { Text "D:/FPGAtest/speaker/speaker.v" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.60 % " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns 26.40 % " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0}  } { { "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" "" { Report "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/FPGAtest/speaker/db/speaker.quartus_db" { Floorplan "D:/FPGAtest/speaker/" "" "2.962 ns" { clk speaker~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 speaker~reg0 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.962 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 44 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 44; CLK Node = 'clk'" {  } { { "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" "" { Report "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/FPGAtest/speaker/db/speaker.quartus_db" { Floorplan "D:/FPGAtest/speaker/" "" "" { clk } "NODE_NAME" } "" } } { "speaker.v" "" { Text "D:/FPGAtest/speaker/speaker.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns counter\[4\] 2 REG LC_X33_Y14_N5 4 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X33_Y14_N5; Fanout = 4; REG Node = 'counter\[4\]'" {  } { { "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" "" { Report "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/FPGAtest/speaker/db/speaker.quartus_db" { Floorplan "D:/FPGAtest/speaker/" "" "1.493 ns" { clk counter[4] } "NODE_NAME" } "" } } { "speaker.v" "" { Text "D:/FPGAtest/speaker/speaker.v" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.60 % " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns 26.40 % " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0}  } { { "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" "" { Report "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/FPGAtest/speaker/db/speaker.quartus_db" { Floorplan "D:/FPGAtest/speaker/" "" "2.962 ns" { clk counter[4] } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 counter[4] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" "" { Report "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/FPGAtest/speaker/db/speaker.quartus_db" { Floorplan "D:/FPGAtest/speaker/" "" "2.962 ns" { clk speaker~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 speaker~reg0 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" "" { Report "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/FPGAtest/speaker/db/speaker.quartus_db" { Floorplan "D:/FPGAtest/speaker/" "" "2.962 ns" { clk counter[4] } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 counter[4] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "speaker.v" "" { Text "D:/FPGAtest/speaker/speaker.v" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "speaker.v" "" { Text "D:/FPGAtest/speaker/speaker.v" 16 -1 0 } }  } 0}  } { { "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" "" { Report "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/FPGAtest/speaker/db/speaker.quartus_db" { Floorplan "D:/FPGAtest/speaker/" "" "4.847 ns" { counter[4] reduce_nor~101 reduce_nor~103 speaker~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "4.847 ns" { counter[4] reduce_nor~101 reduce_nor~103 speaker~reg0 } { 0.000ns 1.167ns 0.437ns 1.196ns } { 0.000ns 0.590ns 0.590ns 0.867ns } } } { "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" "" { Report "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/FPGAtest/speaker/db/speaker.quartus_db" { Floorplan "D:/FPGAtest/speaker/" "" "2.962 ns" { clk speaker~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 speaker~reg0 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" "" { Report "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/FPGAtest/speaker/db/speaker.quartus_db" { Floorplan "D:/FPGAtest/speaker/" "" "2.962 ns" { clk counter[4] } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 counter[4] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk speaker speaker~reg0 7.602 ns register " "Info: tco from clock \"clk\" to destination pin \"speaker\" through register \"speaker~reg0\" is 7.602 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.962 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 44 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 44; CLK Node = 'clk'" {  } { { "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" "" { Report "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/FPGAtest/speaker/db/speaker.quartus_db" { Floorplan "D:/FPGAtest/speaker/" "" "" { clk } "NODE_NAME" } "" } } { "speaker.v" "" { Text "D:/FPGAtest/speaker/speaker.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns speaker~reg0 2 REG LC_X31_Y13_N3 2 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X31_Y13_N3; Fanout = 2; REG Node = 'speaker~reg0'" {  } { { "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" "" { Report "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/FPGAtest/speaker/db/speaker.quartus_db" { Floorplan "D:/FPGAtest/speaker/" "" "1.493 ns" { clk speaker~reg0 } "NODE_NAME" } "" } } { "speaker.v" "" { Text "D:/FPGAtest/speaker/speaker.v" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.60 % " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns 26.40 % " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0}  } { { "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" "" { Report "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/FPGAtest/speaker/db/speaker.quartus_db" { Floorplan "D:/FPGAtest/speaker/" "" "2.962 ns" { clk speaker~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 speaker~reg0 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "speaker.v" "" { Text "D:/FPGAtest/speaker/speaker.v" 16 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.416 ns + Longest register pin " "Info: + Longest register to pin delay is 4.416 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns speaker~reg0 1 REG LC_X31_Y13_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y13_N3; Fanout = 2; REG Node = 'speaker~reg0'" {  } { { "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" "" { Report "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/FPGAtest/speaker/db/speaker.quartus_db" { Floorplan "D:/FPGAtest/speaker/" "" "" { speaker~reg0 } "NODE_NAME" } "" } } { "speaker.v" "" { Text "D:/FPGAtest/speaker/speaker.v" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.292 ns) + CELL(2.124 ns) 4.416 ns speaker 2 PIN PIN_138 0 " "Info: 2: + IC(2.292 ns) + CELL(2.124 ns) = 4.416 ns; Loc. = PIN_138; Fanout = 0; PIN Node = 'speaker'" {  } { { "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" "" { Report "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/FPGAtest/speaker/db/speaker.quartus_db" { Floorplan "D:/FPGAtest/speaker/" "" "4.416 ns" { speaker~reg0 speaker } "NODE_NAME" } "" } } { "speaker.v" "" { Text "D:/FPGAtest/speaker/speaker.v" 3 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 48.10 % " "Info: Total cell delay = 2.124 ns ( 48.10 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.292 ns 51.90 % " "Info: Total interconnect delay = 2.292 ns ( 51.90 % )" {  } {  } 0}  } { { "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" "" { Report "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/FPGAtest/speaker/db/speaker.quartus_db" { Floorplan "D:/FPGAtest/speaker/" "" "4.416 ns" { speaker~reg0 speaker } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "4.416 ns" { speaker~reg0 speaker } { 0.000ns 2.292ns } { 0.000ns 2.124ns } } }  } 0}  } { { "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" "" { Report "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/FPGAtest/speaker/db/speaker.quartus_db" { Floorplan "D:/FPGAtest/speaker/" "" "2.962 ns" { clk speaker~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 speaker~reg0 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" "" { Report "D:/FPGAtest/speaker/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/FPGAtest/speaker/db/speaker.quartus_db" { Floorplan "D:/FPGAtest/speaker/" "" "4.416 ns" { speaker~reg0 speaker } "NODE_NAME" } "" } } { "c:/altera/quartus501/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus501/bin/Technology_Viewer.qrui" "4.416 ns" { speaker~reg0 speaker } { 0.000ns 2.292ns } { 0.000ns 2.124ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jan 18 19:58:03 2008 " "Info: Processing ended: Fri Jan 18 19:58:03 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}