speaker.map.summary

verilog语言写的杨声器!

Flow Status : Successful - Fri Jan 18 19:57:42 2008
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : speaker
Top-level Entity Name : music
Family : Cyclone
Device : EP1C6Q240C8
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 72
Total pins : 2
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 0