dds.vhd.bak

实现任意小数分频的VHDL源代码,我自己写的,仿真结果是正确的,希望对大家有用!我是打算将400M的时钟分为57.344M

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dds is
port(
     inclk: in std_logic;--400MHz
     rst: in std_logic;
     aclr: in std_logic;
    
     
     outdata: buffer std_logic_vector(15 downto 0);
     outclk: out std_logic
     );
end dds;


architecture behave of dds is
signal cnt_clk: std_logic_vector(15 downto 0);

begin
 
 process(inclk)
  begin

   if (rst='1') then
    cnt_clk <="0000000000000000";
   elsif rising_edge(inclk) then
      cnt_clk<=cnt_clk+"0010010010110001";
     if cnt_clk="1111111111111111" then
       outclk<=outdata(15);
     
     end if;
   end if;
 end process;
end behave;