dds.fit.summary

实现任意小数分频的VHDL源代码,我自己写的,仿真结果是正确的,希望对大家有用!我是打算将400M的时钟分为57.344M

Fitter Status : Successful - Wed Jan 16 17:38:42 2008
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version
Revision Name : DDS
Top-level Entity Name : DDS
Family : Cyclone II
Device : EP2C20F484C8
Timing Models : Final
Total logic elements : 16 / 18,752 ( < 1 % )
    Total combinational functions : 16 / 18,752 ( < 1 % )
    Dedicated logic registers : 16 / 18,752 ( < 1 % )
Total registers : 16
Total pins : 20 / 315 ( 6 % )
Total virtual pins : 0
Total memory bits : 0 / 239,616 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )