📄 dds.sim.rpt
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; |DDS|fcw[6] ; |DDS|fcw[6] ; out ;
; |DDS|fcw[5] ; |DDS|fcw[5] ; out ;
; |DDS|fcw[4] ; |DDS|fcw[4] ; out ;
; |DDS|fcw[3] ; |DDS|fcw[3] ; out ;
; |DDS|fcw[2] ; |DDS|fcw[2] ; out ;
; |DDS|fcw[1] ; |DDS|fcw[1] ; out ;
; |DDS|fcw[0] ; |DDS|fcw[0] ; out ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~85 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~85 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~86 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~86 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~90 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~90 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~91 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~91 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~95 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~95 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~96 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~96 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~110 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~110 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~111 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~111 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~120 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~120 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~121 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~121 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~125 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~125 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~126 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~126 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~135 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~135 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~136 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~136 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~140 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~140 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~141 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~141 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~150 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~150 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~151 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~151 ; out0 ;
+----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------+------------------+
; |DDS|rst ; |DDS|rst ; out ;
; |DDS|aclr ; |DDS|aclr ; out ;
; |DDS|fcw[15] ; |DDS|fcw[15] ; out ;
; |DDS|fcw[14] ; |DDS|fcw[14] ; out ;
; |DDS|fcw[13] ; |DDS|fcw[13] ; out ;
; |DDS|fcw[12] ; |DDS|fcw[12] ; out ;
; |DDS|fcw[11] ; |DDS|fcw[11] ; out ;
; |DDS|fcw[10] ; |DDS|fcw[10] ; out ;
; |DDS|fcw[9] ; |DDS|fcw[9] ; out ;
; |DDS|fcw[8] ; |DDS|fcw[8] ; out ;
; |DDS|fcw[7] ; |DDS|fcw[7] ; out ;
; |DDS|fcw[6] ; |DDS|fcw[6] ; out ;
; |DDS|fcw[5] ; |DDS|fcw[5] ; out ;
; |DDS|fcw[4] ; |DDS|fcw[4] ; out ;
; |DDS|fcw[3] ; |DDS|fcw[3] ; out ;
; |DDS|fcw[2] ; |DDS|fcw[2] ; out ;
; |DDS|fcw[1] ; |DDS|fcw[1] ; out ;
; |DDS|fcw[0] ; |DDS|fcw[0] ; out ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~85 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~85 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~86 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~86 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~90 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~90 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~91 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~91 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~95 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~95 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~96 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~96 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~110 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~110 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~111 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~111 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~120 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~120 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~121 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~121 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~125 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~125 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~126 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~126 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~135 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~135 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~136 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~136 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~140 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~140 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~141 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~141 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~150 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~150 ; out0 ;
; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~151 ; |DDS|lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|op_1~151 ; out0 ;
+----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
Info: Processing started: Wed Jan 16 17:52:07 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off DDS -c DDS
Info: Using vector source file "C:/Documents and Settings/Administrator/桌面/DDS小数分频/DDS.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 66.97 %
Info: Number of transitions in simulation is 29401
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
Info: Allocated 92 megabytes of memory during processing
Info: Processing ended: Wed Jan 16 17:52:08 2008
Info: Elapsed time: 00:00:01
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