dds.tan.summary

实现任意小数分频的VHDL源代码,我自己写的,仿真结果是正确的,希望对大家有用!我是打算将400M的时钟分为57.344M

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 6.783 ns
From           : fcw[1]
To             : lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[15]
From Clock     : --
To Clock       : inclk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 10.542 ns
From           : lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[15]
To             : outclk
From Clock     : inclk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -3.235 ns
From           : fcw[13]
To             : lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[13]
From Clock     : --
To Clock       : inclk
Failed Paths   : 0

Type           : Clock Setup: 'inclk'
Slack          : N/A
Required Time  : None
Actual Time    : 311.43 MHz ( period = 3.211 ns )
From           : lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[0]
To             : lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[15]
From Clock     : inclk
To Clock       : inclk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------