prev_cmp_dds.qmsg

实现任意小数分频的VHDL源代码,我自己写的,仿真结果是正确的,希望对大家有用!我是打算将400M的时钟分为57.344M

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jan 16 17:40:34 2008 " "Info: Processing started: Wed Jan 16 17:40:34 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DDS -c DDS --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DDS -c DDS --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DDS.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file DDS.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 DDS " "Info: Found entity 1: DDS" {  } { { "DDS.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/DDS小数分频/DDS.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "DDS " "Info: Elaborating entity \"DDS\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_add_sub2.tdf 1 1 " "Warning: Using design file lpm_add_sub2.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub2 " "Info: Found entity 1: lpm_add_sub2" {  } { { "lpm_add_sub2.tdf" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS小数分频/lpm_add_sub2.tdf" 39 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub2 lpm_add_sub2:inst " "Info: Elaborating entity \"lpm_add_sub2\" for hierarchy \"lpm_add_sub2:inst\"" {  } { { "DDS.bdf" "inst" { Schematic "C:/Documents and Settings/Administrator/桌面/DDS小数分频/DDS.bdf" { { 176 304 464 304 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../altera/71/quartus/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../altera/71/quartus/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/lpm_add_sub.tdf" 102 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub lpm_add_sub2:inst\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"lpm_add_sub2:inst\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "lpm_add_sub2.tdf" "lpm_add_sub_component" { Text "C:/Documents and Settings/Administrator/桌面/DDS小数分频/lpm_add_sub2.tdf" 51 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub2:inst\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborated megafunction instantiation \"lpm_add_sub2:inst\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "lpm_add_sub2.tdf" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS小数分频/lpm_add_sub2.tdf" 51 2 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_9mh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_9mh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_9mh " "Info: Found entity 1: add_sub_9mh" {  } { { "db/add_sub_9mh.tdf" "" { Text "C:/Documents and Settings/Administrator/桌面/DDS小数分频/db/add_sub_9mh.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_9mh lpm_add_sub2:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_9mh:auto_generated " "Info: Elaborating entity \"add_sub_9mh\" for hierarchy \"lpm_add_sub2:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_9mh:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/altera/71/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 1  Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "134 " "Info: Allocated 134 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jan 16 17:40:35 2008 " "Info: Processing ended: Wed Jan 16 17:40:35 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}