dds.vhd

实现任意小数分频的VHDL源代码,我自己写的,仿真结果是正确的,希望对大家有用!我是打算将400M的时钟分为57.344M

-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 7.1 Build 156 04/30/2007 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY DDS IS 
	port
	(
		inclk :  IN  STD_LOGIC;
		rst :  IN  STD_LOGIC;
		aclr :  IN  STD_LOGIC;
		fcw :  IN  STD_LOGIC_VECTOR(15 downto 0);
		outclk :  OUT  STD_LOGIC
	);
END DDS;

ARCHITECTURE bdf_type OF DDS IS 

component lpm_add_sub2
	PORT(clock : IN STD_LOGIC;
		 clken : IN STD_LOGIC;
		 aclr : IN STD_LOGIC;
		 dataa : IN STD_LOGIC_VECTOR(15 downto 0);
		 datab : IN STD_LOGIC_VECTOR(15 downto 0);
		 result : OUT STD_LOGIC_VECTOR(15 downto 0)
	);
end component;

signal	outdata :  STD_LOGIC_VECTOR(15 downto 0);


BEGIN 



b2v_inst : lpm_add_sub2
PORT MAP(clock => inclk,
		 clken => rst,
		 aclr => aclr,
		 dataa => outdata,
		 datab => fcw,
		 result => outdata);
outclk <= outdata(15);

END;