新建 文本文档 (4).txt

来自「基于VHDL的电子钟」· 文本 代码 · 共 141 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sj is
port(clk1,clk2,clr:in std_logic;
	selout:out std_logic_vector(2 downto 0);
	j:out std_logic_vector(6 downto 0));
end sj;

architecture mz of sj is
	signal co, co1:std_logic:='0';
	signal a,b,c,d,e,f,g:std_logic_vector(3 downto 0);
	signal  sele,h:std_logic_vector(2 downto 0);
begin
	process(clk1,clr)
	begin
		if(clr='1')then
			b<="0000";
			a<="0000";
		elsif(clk1'event and clk1='1')then
			if(b="1001")then
				b<="0000";
					if(a="0101")then
					   a<="0000";
					   co<='1';
					else
					   a<=a+1;
					   co<='0';
					end if;
				else
					b<=b+1;
				end if;
			else
				null;
			end if;
			end process;

process(co,clr)
	begin
			if(clr='1')then
			   c<="0000";
			   d<="0000";
			elsif(co'event and co='1')then
				if(d="1001")then
				   d<="0000";
					if(c="0101")then
					   c<="0000";
					   co1<='1';
					else
					   c<=c+1;
					   co1<='0';
					end if;
				else
					d<=d+1;
				end if;
			else null;
			end if;
			end process;
			process(co1,clr)
			begin
			if(clr='1')then
				e<="0000";
				f<="0000";
			elsif(co1'event and co1='1')then
				if(f="0011"and e="0010")then
					f<="0000";
					e<="0000";
				elsif(f="1001")then
					f<="0000";
					e<=e+1;
				else
					f<=f+1;
				end if;
 			
		else
			null;
		end if;
	end process;

process(a,b,c,d,e,f,h)
begin
	
	if(h="000")then
	   g<=b;
	elsif(h="001")then
		g<=a;
	elsif(h="010")then
		g<=d;
	elsif(h="011")then
		g<=c;
	elsif(h="100")then
		g<=f;
	elsif(h="101")then
		g<=e;
	else
	   null;
	end if;
	end process;
process(clk2)


begin
	if(clk2'event and clk2='1')then
		if(sele="000")then
			sele<="001";
		elsif(sele="001")then
			sele<="010";
		elsif(sele="010")then
			sele<="011";
		elsif(sele="011")then
			sele<="100";
		elsif(sele="100")then
			sele<="101";
		else
			sele<="000";
		end if;
	end if;
	h<=sele;
end process;
process(g)
begin
	case g is
	when"0000"=>j<="1111110";
	when"0001"=>j<="0110000";
	when"0010"=>j<="1101101";
	when"0011"=>j<="1111001";
	when"0100"=>j<="0110011";
	when"0101"=>j<="1011011";
	when"0110"=>j<="1011111";
	when"0111"=>j<="1110000";
	when"1000"=>j<="1111111";
	when others=>j<="1111011";
end case;
end process;
process(h)
begin
selout<=h;
end process;

end mz;