📄 test.rpt
字号:
- 5 - A 22 OR2 0 4 0 2 |LPM_ADD_SUB:527|addcore:adder|:99
- 1 - A 22 OR2 0 4 0 2 |LPM_ADD_SUB:527|addcore:adder|:103
- 2 - A 13 OR2 0 4 0 2 |LPM_ADD_SUB:527|addcore:adder|:107
- 3 - A 13 OR2 0 4 0 2 |LPM_ADD_SUB:527|addcore:adder|:111
- 4 - A 13 OR2 0 4 0 2 |LPM_ADD_SUB:527|addcore:adder|:115
- 1 - A 13 OR2 0 4 0 2 |LPM_ADD_SUB:527|addcore:adder|:119
- 2 - A 23 OR2 0 4 0 3 |LPM_ADD_SUB:527|addcore:adder|:123
- 4 - A 23 AND2 0 4 0 2 |LPM_ADD_SUB:527|addcore:adder|:131
- 8 - A 20 DFFE + 0 2 0 14 CLKK (:7)
- 2 - A 18 DFFE + 0 2 1 0 TXDH (:8)
- 8 - A 19 DFFE 0 3 1 0 TXDF (:9)
- 7 - A 20 DFFE + 0 2 0 1 time6 (:10)
- 6 - A 20 DFFE + 0 3 0 2 time5 (:11)
- 4 - A 20 DFFE + 0 2 0 3 time4 (:12)
- 8 - A 14 DFFE + 0 2 0 2 time3 (:13)
- 7 - A 14 DFFE + 0 3 0 2 time2 (:14)
- 5 - A 14 DFFE + 0 2 0 3 time1 (:15)
- 6 - A 14 DFFE + 0 1 0 4 time0 (:16)
- 2 - A 20 OR2 0 2 0 6 :48
- 1 - A 20 OR2 0 4 0 3 :53
- 1 - A 14 OR2 s 0 3 0 1 ~55~1
- 3 - A 18 DFFE + 0 3 0 10 time6~162 (:162)
- 4 - A 18 DFFE + 0 3 0 10 time5~162 (:163)
- 8 - A 18 DFFE + 0 3 0 2 time4~162 (:164)
- 6 - A 18 DFFE + 0 3 0 1 time3~162 (:165)
- 1 - A 18 DFFE + 0 3 0 1 time2~162 (:166)
- 3 - A 16 DFFE + 0 3 0 1 time1~162 (:167)
- 2 - A 16 DFFE + 0 2 0 2 time0~162 (:168)
- 3 - A 23 DFFE 0 4 0 22 time12 (:314)
- 5 - A 23 DFFE 0 3 0 2 time11 (:315)
- 7 - A 23 DFFE 0 4 0 2 time10 (:316)
- 6 - A 23 DFFE 0 3 0 3 time9 (:317)
- 1 - A 23 DFFE 0 4 0 2 time8 (:318)
- 5 - A 13 DFFE 0 4 0 2 time7 (:319)
- 7 - A 13 DFFE 0 4 0 2 time6~237 (:320)
- 6 - A 13 DFFE 0 4 0 2 time5~237 (:321)
- 7 - A 19 DFFE 0 4 0 2 time4~237 (:322)
- 7 - A 22 DFFE 0 4 0 2 time3~237 (:323)
- 6 - A 22 DFFE 0 4 0 2 time2~237 (:324)
- 8 - A 22 DFFE 0 4 0 2 time1~237 (:325)
- 5 - A 20 DFFE 0 3 0 3 time0~237 (:326)
- 8 - A 23 AND2 s 0 3 0 1 ~370~1
- 2 - A 22 OR2 0 4 0 19 :370
- 8 - A 13 OR2 s 0 4 0 1 ~388~1
- 3 - A 22 OR2 s 0 4 0 1 ~388~2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\test\test.rpt
test
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 0/ 48( 0%) 17/ 48( 35%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\test\test.rpt
test
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 16 clk
DFF 15 CLKK
Device-Specific Information: c:\test\test.rpt
test
** EQUATIONS **
clk : INPUT;
-- Node name is 'AD_RAM_LED1'
-- Equation name is 'AD_RAM_LED1', type is output
AD_RAM_LED1 = TXDF;
-- Node name is 'AD_RAM_LED2'
-- Equation name is 'AD_RAM_LED2', type is output
AD_RAM_LED2 = VCC;
-- Node name is 'AD_RAM_LED3'
-- Equation name is 'AD_RAM_LED3', type is output
AD_RAM_LED3 = VCC;
-- Node name is 'AD_RAM_LED4'
-- Equation name is 'AD_RAM_LED4', type is output
AD_RAM_LED4 = VCC;
-- Node name is ':7' = 'CLKK'
-- Equation name is 'CLKK', location is LC8_A20, type is buried.
CLKK = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = CLKK & _LC1_A20
# CLKK & !_LC3_A20
# !CLKK & !_LC1_A20 & _LC3_A20;
-- Node name is ':168' = 'time0~162'
-- Equation name is 'time0~162', location is LC2_A16, type is buried.
time0~162 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !time0~162
# time5~162 & time6~162;
-- Node name is ':326' = 'time0~237'
-- Equation name is 'time0~237', location is LC5_A20, type is buried.
time0~237 = DFFE( _EQ003, CLKK, VCC, VCC, VCC);
_EQ003 = !time0~237
# !_LC2_A22 & time12;
-- Node name is ':16' = 'time0'
-- Equation name is 'time0', location is LC6_A14, type is buried.
time0 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = _LC2_A20 & !time0;
-- Node name is ':167' = 'time1~162'
-- Equation name is 'time1~162', location is LC3_A16, type is buried.
time1~162 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = time0~162 & !time1~162 & !time5~162
# time0~162 & !time1~162 & !time6~162
# !time0~162 & time1~162 & !time5~162
# !time0~162 & time1~162 & !time6~162;
-- Node name is ':325' = 'time1~237'
-- Equation name is 'time1~237', location is LC8_A22, type is buried.
time1~237 = DFFE( _EQ006, CLKK, VCC, VCC, VCC);
_EQ006 = time0~237 & !time1~237 & !time12
# _LC2_A22 & time0~237 & !time1~237
# !time0~237 & time1~237 & !time12
# _LC2_A22 & !time0~237 & time1~237;
-- Node name is ':15' = 'time1'
-- Equation name is 'time1', location is LC5_A14, type is buried.
time1 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = _LC2_A20 & time0 & !time1
# _LC2_A20 & !time0 & time1;
-- Node name is ':166' = 'time2~162'
-- Equation name is 'time2~162', location is LC1_A18, type is buried.
time2~162 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = _LC1_A16 & !time2~162
# _LC1_A16 & time5~162 & time6~162
# !_LC1_A16 & time2~162 & !time5~162
# !_LC1_A16 & time2~162 & !time6~162;
-- Node name is ':324' = 'time2~237'
-- Equation name is 'time2~237', location is LC6_A22, type is buried.
time2~237 = DFFE( _EQ009, CLKK, VCC, VCC, VCC);
_EQ009 = !_LC4_A22 & time2~237 & !time12
# _LC2_A22 & !_LC4_A22 & time2~237
# _LC4_A22 & !time2~237
# !_LC2_A22 & _LC4_A22 & time12;
-- Node name is ':14' = 'time2'
-- Equation name is 'time2', location is LC7_A14, type is buried.
time2 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = _LC2_A20 & !time0 & time2
# _LC2_A20 & !time1 & time2
# _LC2_A20 & time0 & time1 & !time2;
-- Node name is ':165' = 'time3~162'
-- Equation name is 'time3~162', location is LC6_A18, type is buried.
time3~162 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = _LC5_A18 & !time3~162
# _LC5_A18 & time5~162 & time6~162
# !_LC5_A18 & time3~162 & !time5~162
# !_LC5_A18 & time3~162 & !time6~162;
-- Node name is ':323' = 'time3~237'
-- Equation name is 'time3~237', location is LC7_A22, type is buried.
time3~237 = DFFE( _EQ012, CLKK, VCC, VCC, VCC);
_EQ012 = !_LC5_A22 & time3~237 & !time12
# _LC2_A22 & !_LC5_A22 & time3~237
# _LC5_A22 & !time3~237
# !_LC2_A22 & _LC5_A22 & time12;
-- Node name is ':13' = 'time3'
-- Equation name is 'time3', location is LC8_A14, type is buried.
time3 = DFFE( _EQ013, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = _LC2_A20 & !_LC3_A14 & time3
# _LC2_A20 & _LC3_A14 & !time3;
-- Node name is ':164' = 'time4~162'
-- Equation name is 'time4~162', location is LC8_A18, type is buried.
time4~162 = DFFE( _EQ014, GLOBAL( clk), VCC, VCC, VCC);
_EQ014 = _LC7_A18 & !time4~162
# _LC7_A18 & time5~162 & time6~162
# !_LC7_A18 & time4~162 & !time5~162
# !_LC7_A18 & time4~162 & !time6~162;
-- Node name is ':322' = 'time4~237'
-- Equation name is 'time4~237', location is LC7_A19, type is buried.
time4~237 = DFFE( _EQ015, CLKK, VCC, VCC, VCC);
_EQ015 = !_LC1_A22 & time4~237 & !time12
# !_LC1_A22 & _LC2_A22 & time4~237
# _LC1_A22 & !time4~237
# _LC1_A22 & !_LC2_A22 & time12;
-- Node name is ':12' = 'time4'
-- Equation name is 'time4', location is LC4_A20, type is buried.
time4 = DFFE( _EQ016, GLOBAL( clk), VCC, VCC, VCC);
_EQ016 = !_LC2_A14 & _LC2_A20 & time4
# _LC2_A14 & _LC2_A20 & !time4;
-- Node name is ':163' = 'time5~162'
-- Equation name is 'time5~162', location is LC4_A18, type is buried.
time5~162 = DFFE( _EQ017, GLOBAL( clk), VCC, VCC, VCC);
_EQ017 = _LC7_A18 & time4~162 & !time5~162
# !time4~162 & time5~162 & !time6~162
# !_LC7_A18 & time5~162 & !time6~162;
-- Node name is ':321' = 'time5~237'
-- Equation name is 'time5~237', location is LC6_A13, type is buried.
time5~237 = DFFE( _EQ018, CLKK, VCC, VCC, VCC);
_EQ018 = !_LC2_A13 & time5~237 & !time12
# !_LC2_A13 & _LC2_A22 & time5~237
# _LC2_A13 & !time5~237
# _LC2_A13 & !_LC2_A22 & time12;
-- Node name is ':11' = 'time5'
-- Equation name is 'time5', location is LC6_A20, type is buried.
time5 = DFFE( _EQ019, GLOBAL( clk), VCC, VCC, VCC);
_EQ019 = _LC2_A20 & !time4 & time5
# !_LC2_A14 & _LC2_A20 & time5
# _LC2_A14 & _LC2_A20 & time4 & !time5;
-- Node name is ':162' = 'time6~162'
-- Equation name is 'time6~162', location is LC3_A18, type is buried.
time6~162 = DFFE( _EQ020, GLOBAL( clk), VCC, VCC, VCC);
_EQ020 = _LC7_A18 & time4~162 & time5~162 & !time6~162
# !time5~162 & time6~162;
-- Node name is ':320' = 'time6~237'
-- Equation name is 'time6~237', location is LC7_A13, type is buried.
time6~237 = DFFE( _EQ021, CLKK, VCC, VCC, VCC);
_EQ021 = !_LC3_A13 & time6~237 & !time12
# _LC2_A22 & !_LC3_A13 & time6~237
# _LC3_A13 & !time6~237
# !_LC2_A22 & _LC3_A13 & time12;
-- Node name is ':10' = 'time6'
-- Equation name is 'time6', location is LC7_A20, type is buried.
time6 = DFFE( _EQ022, GLOBAL( clk), VCC, VCC, VCC);
_EQ022 = _LC1_A20 & _LC3_A20;
-- Node name is ':319' = 'time7'
-- Equation name is 'time7', location is LC5_A13, type is buried.
time7 = DFFE( _EQ023, CLKK, VCC, VCC, VCC);
_EQ023 = !_LC4_A13 & time7 & !time12
# _LC2_A22 & !_LC4_A13 & time7
# _LC4_A13 & !time7
# !_LC2_A22 & _LC4_A13 & time12;
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