test.vhd

来自「为FPGA系统所设计的一个简单的控制LED灯显示的小程序」· VHDL 代码 · 共 68 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; 

ENTITY test IS
   PORT (
      AD_RAM_LED1:              OUT STD_LOGIC;
      AD_RAM_LED2:              OUT STD_LOGIC;
      AD_RAM_LED3:              OUT STD_LOGIC;
      AD_RAM_LED4:              OUT STD_LOGIC;
      clk                     : IN std_Ulogic ; 
      txd                     : OUT std_Ulogic --串行数据发送端      
      );
END test;

ARCHITECTURE arch OF test IS
SIGNAL TXDF:            std_Ulogic;
SIGNAL TXDH:            std_Ulogic;
SIGNAL CLKK                :STD_LOGIC;
BEGIN
AD_RAM_LED1<=TXDF;
txd<=TXDH;
AD_RAM_LED2<='1';
AD_RAM_LED3<='1';
AD_RAM_LED4<='1';

PROCESS(CLK)
VARIABLE time : integer range 0 to 100 :=0; 
BEGIN
  IF CLK'EVENT AND CLK='1'THEN       
       TIME := TIME + 1;
       IF TIME >= 100 THEN 
        TIME := 0;  
        CLKK <= not CLKK;
       END IF;
       END IF;       
end process;

PROCESS(CLK)
VARIABLE time : integer range 0 to 96 :=0; 
BEGIN
  IF CLK'EVENT AND CLK='1'THEN       
       IF TIME >= 96 THEN 
        TIME := 0;  
        TXDH <= not TXDH;
       END IF;
        TIME := TIME + 1;
       END IF;       
end process;


PROCESS(CLKK)
VARIABLE time : integer range 0 to 4608 :=0; 
BEGIN
  IF CLKK'EVENT AND CLKK='1'THEN       
       IF TIME >= 4607 THEN 
        TIME := 0;  
         TXDF<= not TXDF;
       END IF;
     TIME := TIME + 1;
       END IF;
       
end process;

END arch;