t_div5.vhd

来自「是基于EDA系统上的一24小时制的数字钟设计」· VHDL 代码 · 共 25 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY t_div5 IS
PORT(clk:IN STD_LOGIC;
     q:OUT STD_LOGIC);
END t_div5;
ARCHITECTURE rt1 OF t_div5 IS
SIGNAL count:STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL q0:STD_LOGIC;
BEGIN
 PROCESS(clk)
BEGIN
 IF clk='1' and clk'event THEN
  IF count="100" THEN
     count<="000";
     q0<='1';
   ELSE
     count<=count+'1';
     q0<='0';
   END IF;
  END IF;
END PROCESS;
q<=q0;
END rt1;