t_count24.vhd

来自「是基于EDA系统上的一24小时制的数字钟设计」· VHDL 代码 · 共 32 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY t_count24 IS
PORT(clk:IN STD_LOGIC;
     bcd10_out,bcd1_out:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0));
END t_count24;
ARCHITECTURE rt1 OF t_count24 IS
BEGIN
 PROCESS(clk,bcd10_out)
BEGIN
 IF clk='1' and clk'event THEN
  IF bcd10_out="0010" AND bcd1_out="0011" THEN
      bcd1_out<="0000";
  ELSIF bcd1_out="1001" THEN
      bcd1_out<="0000";
  ELSE 
      bcd1_out<=bcd1_out+'1';
  END IF;
 END IF;
END PROCESS;
 PROCESS(clk,bcd1_out)
BEGIN
 IF clk='1' AND clk'event THEN
  IF bcd1_out="0011" AND bcd10_out="0010" THEN
      bcd10_out<="0000";
  ELSIF bcd1_out="1001" THEN
      bcd10_out<=bcd10_out+'1';
  END IF;
 END IF;
END PROCESS;
END rt1;