📄 display.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY display IS
PORT(din0:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
din1:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
din2:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
din3:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
din4:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
din5:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CLK: IN STD_LOGIC;
LED_SA: OUT STD_LOGIC;
LED_SB: OUT STD_LOGIC;
LED_SC: OUT STD_LOGIC;
LED_A: OUT STD_LOGIC;
LED_B: OUT STD_LOGIC;
LED_C: OUT STD_LOGIC;
LED_D: OUT STD_LOGIC;
LED_E: OUT STD_LOGIC;
LED_F: OUT STD_LOGIC;
LED_G: OUT STD_LOGIC;
LED_DP: OUT STD_LOGIC);
END display;
ARCHITECTURE behave OF display IS
SIGNAL SEG:STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL SEL:STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL NUM:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL s:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
led_sa<=sel(0);
led_sb<=sel(1);
led_sc<=sel(2);
led_a<=seg(0);
led_b<=seg(1);
led_c<=seg(2);
led_d<=seg(3);
led_e<=seg(4);
led_f<=seg(5);
led_g<=seg(6);
PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
IF S="101" THEN
S<="000";
ELSE
s<=s+'1';
END IF;
END IF;
END PROCESS;
PROCESS(s,din0,din1,din2,din3,din4,din5)
BEGIN
IF s="000" THEN
sel<="000";
num<=din0;
led_dp<='0';
ELSIF s="001" THEN
sel<="001";
num<=din1;
led_dp<='0';
ELSIF s="010" THEN
sel<="010";
num<=din2;
led_dp<='0';
ELSIF s="011" THEN
sel<="011";
num<=din3;
led_dp<='0';
ELSIF s="100" THEN
sel<="100";
num<=din4;
led_dp<='0';
ELSIF s="101" THEN
sel<="101";
num<=din5;
led_dp<='0';
ELSE
sel<="XXX";
num<="XXXX";
led_dp<='0';
END IF;
END PROCESS;
SEG<="0111111" WHEN NUM=0 ELSE
"0000110" WHEN NUM=1 ELSE
"1011011" WHEN NUM=2 ELSE
"1001111" WHEN NUM=3 ELSE
"1100110" WHEN NUM=4 ELSE
"1101101" WHEN NUM=5 ELSE
"1111101" WHEN NUM=6 ELSE
"0000111" WHEN NUM=7 ELSE
"1111111" WHEN NUM=8 ELSE
"1101111" WHEN NUM=9 ELSE
"1110111" WHEN NUM=10 ELSE
"1111100" WHEN NUM=11 ELSE
"0111001" WHEN NUM=12 ELSE
"1011110" WHEN NUM=13 ELSE
"1111001" WHEN NUM=14 ELSE
"1110001" WHEN NUM=15 ELSE
"0000000";
END behave;
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