top1.tan.qmsg

是基于EDA系统上的一24小时制的数字钟设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jan 12 17:40:03 2008 " "Info: Processing started: Sat Jan 12 17:40:03 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off top1 -c top1 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off top1 -c top1 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "display.vhd" "" { Text "E:/课件/大三1/课程设计/top1/display.vhd" 11 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK register register s\[1\] s\[2\] 275.03 MHz Internal " "Info: Clock \"CLK\" Internal fmax is restricted to 275.03 MHz between source register \"s\[1\]\" and destination register \"s\[2\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.246 ns + Longest register register " "Info: + Longest register to register delay is 1.246 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns s\[1\] 1 REG LC_X7_Y12_N0 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y12_N0; Fanout = 10; REG Node = 's\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "" { s[1] } "NODE_NAME" } "" } } { "display.vhd" "" { Text "E:/课件/大三1/课程设计/top1/display.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.639 ns) + CELL(0.607 ns) 1.246 ns s\[2\] 2 REG LC_X7_Y12_N2 11 " "Info: 2: + IC(0.639 ns) + CELL(0.607 ns) = 1.246 ns; Loc. = LC_X7_Y12_N2; Fanout = 11; REG Node = 's\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "1.246 ns" { s[1] s[2] } "NODE_NAME" } "" } } { "display.vhd" "" { Text "E:/课件/大三1/课程设计/top1/display.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.607 ns ( 48.72 % ) " "Info: Total cell delay = 0.607 ns ( 48.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.639 ns ( 51.28 % ) " "Info: Total interconnect delay = 0.639 ns ( 51.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "1.246 ns" { s[1] s[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.246 ns" { s[1] s[2] } { 0.000ns 0.639ns } { 0.000ns 0.607ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.767 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.767 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 3 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 3; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "" { CLK } "NODE_NAME" } "" } } { "display.vhd" "" { Text "E:/课件/大三1/课程设计/top1/display.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.587 ns) + CELL(0.711 ns) 2.767 ns s\[2\] 2 REG LC_X7_Y12_N2 11 " "Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X7_Y12_N2; Fanout = 11; REG Node = 's\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "1.298 ns" { CLK s[2] } "NODE_NAME" } "" } } { "display.vhd" "" { Text "E:/课件/大三1/课程设计/top1/display.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.79 % ) " "Info: Total cell delay = 2.180 ns ( 78.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.587 ns ( 21.21 % ) " "Info: Total interconnect delay = 0.587 ns ( 21.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "2.767 ns" { CLK s[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 s[2] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.767 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.767 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 3 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 3; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "" { CLK } "NODE_NAME" } "" } } { "display.vhd" "" { Text "E:/课件/大三1/课程设计/top1/display.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.587 ns) + CELL(0.711 ns) 2.767 ns s\[1\] 2 REG LC_X7_Y12_N0 10 " "Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X7_Y12_N0; Fanout = 10; REG Node = 's\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "1.298 ns" { CLK s[1] } "NODE_NAME" } "" } } { "display.vhd" "" { Text "E:/课件/大三1/课程设计/top1/display.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.79 % ) " "Info: Total cell delay = 2.180 ns ( 78.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.587 ns ( 21.21 % ) " "Info: Total interconnect delay = 0.587 ns ( 21.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "2.767 ns" { CLK s[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 s[1] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "2.767 ns" { CLK s[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 s[2] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "2.767 ns" { CLK s[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 s[1] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "display.vhd" "" { Text "E:/课件/大三1/课程设计/top1/display.vhd" 42 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "display.vhd" "" { Text "E:/课件/大三1/课程设计/top1/display.vhd" 42 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "1.246 ns" { s[1] s[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.246 ns" { s[1] s[2] } { 0.000ns 0.639ns } { 0.000ns 0.607ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "2.767 ns" { CLK s[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 s[2] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "2.767 ns" { CLK s[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 s[1] } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top1" "UNKNOWN" "V1" "E:/课件/大三1/课程设计/top1/db/top1.quartus_db" { Floorplan "E:/课件/大三1/课程设计/top1/" "" "" { s[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { s[2] } {  } {  } } } { "display.vhd" "" { Text "E:/课件/大三1/课程设计/top1/display.vhd" 42 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}