top1.map.qmsg

是基于EDA系统上的一24小时制的数字钟设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jan 12 17:39:48 2008 " "Info: Processing started: Sat Jan 12 17:39:48 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off top1 -c top1 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top1 -c top1" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file top1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 top1 " "Info: Found entity 1: top1" {  } { { "top1.bdf" "" { Schematic "E:/课件/大三1/课程设计/top1/top1.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top11.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file top11.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 top11 " "Info: Found entity 1: top11" {  } { { "top11.bdf" "" { Schematic "E:/课件/大三1/课程设计/top1/top11.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bs.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file bs.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 bs-bss " "Info: Found design unit 1: bs-bss" {  } { { "bs.vhd" "" { Text "E:/课件/大三1/课程设计/top1/bs.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 bs " "Info: Found entity 1: bs" {  } { { "bs.vhd" "" { Text "E:/课件/大三1/课程设计/top1/bs.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "display.vhd 2 1 " "Warning: Using design file display.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 display-behave " "Info: Found design unit 1: display-behave" {  } { { "display.vhd" "" { Text "E:/课件/大三1/课程设计/top1/display.vhd" 24 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 display " "Info: Found entity 1: display" {  } { { "display.vhd" "" { Text "E:/课件/大三1/课程设计/top1/display.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "display " "Info: Elaborating entity \"display\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "LED_DP GND " "Warning: Pin \"LED_DP\" stuck at GND" {  } { { "display.vhd" "" { Text "E:/课件/大三1/课程设计/top1/display.vhd" 22 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "73 " "Info: Implemented 73 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "25 " "Info: Implemented 25 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "11 " "Info: Implemented 11 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "37 " "Info: Implemented 37 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jan 12 17:39:52 2008 " "Info: Processing ended: Sat Jan 12 17:39:52 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}