t_count60.vhd

来自「是基于EDA系统上的一24小时制的数字钟设计」· VHDL 代码 · 共 47 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY t_count60 IS
PORT(clk:IN STD_LOGIC;
     bcd10,bcd1:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);
     preset:IN STD_LOGIC;
     co:OUT STD_LOGIC);
END t_count60;
ARCHITECTURE rt1 OF t_count60 IS
SIGNAL co_1:STD_LOGIC;
BEGIN
 PROCESS(clk,preset)
BEGIN
 IF preset='0' THEN
    bcd1<="0000";
 ELSE
  IF clk='1' and clk'event THEN
   IF bcd1="1001" THEN
      bcd1<="0000";
   ELSE
      bcd1<=bcd1+'1';
   END IF;
  END IF;
 END IF;
END PROCESS;
 PROCESS(clk,preset,bcd1)
BEGIN
 IF preset='0' THEN
    bcd10<="0000";
    co_1<='0';
 ELSE
  IF clk='1' AND clk'event THEN
   IF bcd1="1000" AND bcd10="0101" THEN
      co_1<='1';
   ELSIF bcd1="1001" AND bcd10="0101" THEN
      bcd10<="0000";
      co_1<='0';
   ELSIF bcd1="1001" THEN
      bcd10<=bcd10+'1';
      co_1<='0';
   END IF;
  END IF;
 END IF;
END PROCESS;
co<=NOT co_1;
END rt1;