uart4.vhm

一个UART的FPGA core

  end component;
  component FD1P3DX
    port(
      D : in std_logic;
      SP : in std_logic;
      CK : in std_logic;
      CD : in std_logic;
      Q : out std_logic;
      QN : out std_logic;
      GSR : in std_logic  );
  end component;
  component AND2
    port(
      A : in std_logic;
      B : in std_logic;
      Z : out std_logic  );
  end component;
begin
  II_mem_0_3: DPR16X2B port map (
      RDO0 => DATAOUT0_FFIN,
      RDO1 => DATAOUT1_FFIN,
      WDO0 => WDO0_11,
      WDO1 => WDO1_11,
      RAD0 => bottom(0),
      RAD1 => bottom(1),
      RAD2 => bottom(2),
      RAD3 => bottom(3),
      WAD0 => top_i(0),
      WAD1 => un1_top_axbxc1_2,
      WAD2 => un1_top_axbxc2_2,
      WAD3 => un1_top_axbxc3_2,
      DI0 => data_in(0),
      DI1 => data_in(1),
      WRE => DEC_WRE3,
      WCK => clk_c,
      GSR => GND);
  II_mem_0_2: DPR16X2B port map (
      RDO0 => DATAOUT2_FFIN,
      RDO1 => DATAOUT3_FFIN,
      WDO0 => WDO0_12,
      WDO1 => WDO1_12,
      RAD0 => bottom(0),
      RAD1 => bottom(1),
      RAD2 => bottom(2),
      RAD3 => bottom(3),
      WAD0 => top_i(0),
      WAD1 => un1_top_axbxc1_2,
      WAD2 => un1_top_axbxc2_2,
      WAD3 => un1_top_axbxc3_2,
      DI0 => data_in(2),
      DI1 => data_in(3),
      WRE => DEC_WRE3,
      WCK => clk_c,
      GSR => GND);
  II_mem_0_1: DPR16X2B port map (
      RDO0 => DATAOUT4_FFIN,
      RDO1 => DATAOUT5_FFIN,
      WDO0 => WDO0_13,
      WDO1 => WDO1_13,
      RAD0 => bottom(0),
      RAD1 => bottom(1),
      RAD2 => bottom(2),
      RAD3 => bottom(3),
      WAD0 => top_i(0),
      WAD1 => un1_top_axbxc1_2,
      WAD2 => un1_top_axbxc2_2,
      WAD3 => un1_top_axbxc3_2,
      DI0 => data_in(4),
      DI1 => data_in(5),
      WRE => DEC_WRE3,
      WCK => clk_c,
      GSR => GND);
  II_mem_0_0: DPR16X2B port map (
      RDO0 => DATAOUT6_FFIN,
      RDO1 => DATAOUT7_FFIN,
      WDO0 => WDO0_14,
      WDO1 => WDO1_14,
      RAD0 => bottom(0),
      RAD1 => bottom(1),
      RAD2 => bottom(2),
      RAD3 => bottom(3),
      WAD0 => top_i(0),
      WAD1 => un1_top_axbxc1_2,
      WAD2 => un1_top_axbxc2_2,
      WAD3 => un1_top_axbxc3_2,
      DI0 => data_in(6),
      DI1 => data_in(7),
      WRE => DEC_WRE3,
      WCK => clk_c,
      GSR => GND);
  II_FF_0: FD1P3DX port map (
      D => DATAOUT0_FFIN,
      SP => un1_EF_1_2,
      CK => clk_c,
      CD => rst_c,
      Q => tsr_tmp(0),
      QN => FF_0_QN_2,
      GSR => VCC);
  II_FF_1: FD1P3DX port map (
      D => DATAOUT1_FFIN,
      SP => un1_EF_1_2,
      CK => clk_c,
      CD => rst_c,
      Q => tsr_tmp(1),
      QN => FF_1_QN_2,
      GSR => VCC);
  II_FF_2: FD1P3DX port map (
      D => DATAOUT2_FFIN,
      SP => un1_EF_1_2,
      CK => clk_c,
      CD => rst_c,
      Q => tsr_tmp(2),
      QN => FF_2_QN_2,
      GSR => VCC);
  II_FF_3: FD1P3DX port map (
      D => DATAOUT3_FFIN,
      SP => un1_EF_1_2,
      CK => clk_c,
      CD => rst_c,
      Q => tsr_tmp(3),
      QN => FF_3_QN_2,
      GSR => VCC);
  II_FF_4: FD1P3DX port map (
      D => DATAOUT4_FFIN,
      SP => un1_EF_1_2,
      CK => clk_c,
      CD => rst_c,
      Q => tsr_tmp(4),
      QN => FF_4_QN_2,
      GSR => VCC);
  II_FF_5: FD1P3DX port map (
      D => DATAOUT5_FFIN,
      SP => un1_EF_1_2,
      CK => clk_c,
      CD => rst_c,
      Q => tsr_tmp(5),
      QN => FF_5_QN_2,
      GSR => VCC);
  II_FF_6: FD1P3DX port map (
      D => DATAOUT6_FFIN,
      SP => un1_EF_1_2,
      CK => clk_c,
      CD => rst_c,
      Q => tsr_tmp(6),
      QN => FF_6_QN_2,
      GSR => VCC);
  II_FF_7: FD1P3DX port map (
      D => DATAOUT7_FFIN,
      SP => un1_EF_1_2,
      CK => clk_c,
      CD => rst_c,
      Q => tsr_tmp(7),
      QN => FF_7_QN_2,
      GSR => VCC);
  II_AND2_t0: AND2 port map (
      A => we_en4,
      B => we_en4,
      Z => DEC_WRE3);
  NN_1 <= '0';
  NN_2 <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity dpram16x8_2_1 is
port(
  tsr_tmp : out std_logic_vector (7 downto 0);
  data_in : in std_logic_vector (7 downto 0);
  top_i : in std_logic_vector (0 downto 0);
  bottom : in std_logic_vector (3 downto 0);
  we_en3 :  in std_logic;
  VCC :  in std_logic;
  rst_c :  in std_logic;
  un1_EF_1_1 :  in std_logic;
  GND :  in std_logic;
  clk_c :  in std_logic;
  un1_top_axbxc3_1 :  in std_logic;
  un1_top_axbxc2_1 :  in std_logic;
  un1_top_axbxc1_1 :  in std_logic);
end dpram16x8_2_1;

architecture beh of dpram16x8_2_1 is
  signal WDO0_7 : std_logic ;
  signal WDO1_7 : std_logic ;
  signal WDO0_8 : std_logic ;
  signal WDO1_8 : std_logic ;
  signal WDO0_9 : std_logic ;
  signal WDO1_9 : std_logic ;
  signal WDO0_10 : std_logic ;
  signal WDO1_10 : std_logic ;
  signal DATAOUT0_FFIN : std_logic ;
  signal FF_0_QN_1 : std_logic ;
  signal DATAOUT1_FFIN : std_logic ;
  signal FF_1_QN_1 : std_logic ;
  signal DATAOUT2_FFIN : std_logic ;
  signal FF_2_QN_1 : std_logic ;
  signal DATAOUT3_FFIN : std_logic ;
  signal FF_3_QN_1 : std_logic ;
  signal DATAOUT4_FFIN : std_logic ;
  signal FF_4_QN_1 : std_logic ;
  signal DATAOUT5_FFIN : std_logic ;
  signal FF_5_QN_1 : std_logic ;
  signal DATAOUT6_FFIN : std_logic ;
  signal FF_6_QN_1 : std_logic ;
  signal DATAOUT7_FFIN : std_logic ;
  signal FF_7_QN_1 : std_logic ;
  signal DEC_WRE3 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  component DPR16X2B
    port(
      RDO0 : out std_logic;
      RDO1 : out std_logic;
      WDO0 : out std_logic;
      WDO1 : out std_logic;
      RAD0 : in std_logic;
      RAD1 : in std_logic;
      RAD2 : in std_logic;
      RAD3 : in std_logic;
      WAD0 : in std_logic;
      WAD1 : in std_logic;
      WAD2 : in std_logic;
      WAD3 : in std_logic;
      DI0 : in std_logic;
      DI1 : in std_logic;
      WRE : in std_logic;
      WCK : in std_logic;
      GSR : in std_logic  );
  end component;
  component FD1P3DX
    port(
      D : in std_logic;
      SP : in std_logic;
      CK : in std_logic;
      CD : in std_logic;
      Q : out std_logic;
      QN : out std_logic;
      GSR : in std_logic  );
  end component;
  component AND2
    port(
      A : in std_logic;
      B : in std_logic;
      Z : out std_logic  );
  end component;
begin
  II_mem_0_3: DPR16X2B port map (
      RDO0 => DATAOUT0_FFIN,
      RDO1 => DATAOUT1_FFIN,
      WDO0 => WDO0_7,
      WDO1 => WDO1_7,
      RAD0 => bottom(0),
      RAD1 => bottom(1),
      RAD2 => bottom(2),
      RAD3 => bottom(3),
      WAD0 => top_i(0),
      WAD1 => un1_top_axbxc1_1,
      WAD2 => un1_top_axbxc2_1,
      WAD3 => un1_top_axbxc3_1,
      DI0 => data_in(0),
      DI1 => data_in(1),
      WRE => DEC_WRE3,
      WCK => clk_c,
      GSR => GND);
  II_mem_0_2: DPR16X2B port map (
      RDO0 => DATAOUT2_FFIN,
      RDO1 => DATAOUT3_FFIN,
      WDO0 => WDO0_8,
      WDO1 => WDO1_8,
      RAD0 => bottom(0),
      RAD1 => bottom(1),
      RAD2 => bottom(2),
      RAD3 => bottom(3),
      WAD0 => top_i(0),
      WAD1 => un1_top_axbxc1_1,
      WAD2 => un1_top_axbxc2_1,
      WAD3 => un1_top_axbxc3_1,
      DI0 => data_in(2),
      DI1 => data_in(3),
      WRE => DEC_WRE3,
      WCK => clk_c,
      GSR => GND);
  II_mem_0_1: DPR16X2B port map (
      RDO0 => DATAOUT4_FFIN,
      RDO1 => DATAOUT5_FFIN,
      WDO0 => WDO0_9,
      WDO1 => WDO1_9,
      RAD0 => bottom(0),
      RAD1 => bottom(1),
      RAD2 => bottom(2),
      RAD3 => bottom(3),
      WAD0 => top_i(0),
      WAD1 => un1_top_axbxc1_1,
      WAD2 => un1_top_axbxc2_1,
      WAD3 => un1_top_axbxc3_1,
      DI0 => data_in(4),
      DI1 => data_in(5),
      WRE => DEC_WRE3,
      WCK => clk_c,
      GSR => GND);
  II_mem_0_0: DPR16X2B port map (
      RDO0 => DATAOUT6_FFIN,
      RDO1 => DATAOUT7_FFIN,
      WDO0 => WDO0_10,
      WDO1 => WDO1_10,
      RAD0 => bottom(0),
      RAD1 => bottom(1),
      RAD2 => bottom(2),
      RAD3 => bottom(3),
      WAD0 => top_i(0),
      WAD1 => un1_top_axbxc1_1,
      WAD2 => un1_top_axbxc2_1,
      WAD3 => un1_top_axbxc3_1,
      DI0 => data_in(6),
      DI1 => data_in(7),
      WRE => DEC_WRE3,
      WCK => clk_c,
      GSR => GND);
  II_FF_0: FD1P3DX port map (
      D => DATAOUT0_FFIN,
      SP => un1_EF_1_1,
      CK => clk_c,
      CD => rst_c,
      Q => tsr_tmp(0),
      QN => FF_0_QN_1,
      GSR => VCC);
  II_FF_1: FD1P3DX port map (
      D => DATAOUT1_FFIN,
      SP => un1_EF_1_1,
      CK => clk_c,
      CD => rst_c,
      Q => tsr_tmp(1),
      QN => FF_1_QN_1,
      GSR => VCC);
  II_FF_2: FD1P3DX port map (
      D => DATAOUT2_FFIN,
      SP => un1_EF_1_1,
      CK => clk_c,
      CD => rst_c,
      Q => tsr_tmp(2),
      QN => FF_2_QN_1,
      GSR => VCC);
  II_FF_3: FD1P3DX port map (
      D => DATAOUT3_FFIN,
      SP => un1_EF_1_1,
      CK => clk_c,
      CD => rst_c,
      Q => tsr_tmp(3),
      QN => FF_3_QN_1,
      GSR => VCC);
  II_FF_4: FD1P3DX port map (
      D => DATAOUT4_FFIN,
      SP => un1_EF_1_1,
      CK => clk_c,
      CD => rst_c,
      Q => tsr_tmp(4),
      QN => FF_4_QN_1,
      GSR => VCC);
  II_FF_5: FD1P3DX port map (
      D => DATAOUT5_FFIN,
      SP => un1_EF_1_1,
      CK => clk_c,
      CD => rst_c,
      Q => tsr_tmp(5),
      QN => FF_5_QN_1,
      GSR => VCC);
  II_FF_6: FD1P3DX port map (
      D => DATAOUT6_FFIN,
      SP => un1_EF_1_1,
      CK => clk_c,
      CD => rst_c,
      Q => tsr_tmp(6),
      QN => FF_6_QN_1,
      GSR => VCC);
  II_FF_7: FD1P3DX port map (
      D => DATAOUT7_FFIN,
      SP => un1_EF_1_1,
      CK => clk_c,
      CD => rst_c,
      Q => tsr_tmp(7),
      QN => FF_7_QN_1,
      GSR => VCC);
  II_AND2_t0: AND2 port map (
      A => we_en3,
      B => we_en3,
      Z => DEC_WRE3);
  NN_1 <= '0';
  NN_2 <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity dpram16x8_1_1 is
port(
  tsr_tmp : out std_logic_vector (7 downto 0);
  data_in : in std_logic_vector (7 downto 0);
  top_i : in std_logic_vector (0 downto 0);
  bottom : in std_logic_vector (3 downto 0);
  we_en2 :  in std_logic;
  VCC :  in std_logic;
  rst_c :  in std_logic;
  un1_EF_1_0 :  in std_logic;
  GND :  in std_logic;
  clk_c :  in std_logic;
  un1_top_axbxc3_0 :  in std_logic;
  un1_top_axbxc2_0 :  in std_logic;
  un1_top_axbxc1_0 :  in std_logic);
end dpram16x8_1_1;

architecture beh of dpram16x8_1_1 is
  signal WDO0_3 : std_logic ;
  signal WDO1_3 : std_logic ;
  signal WDO0_4 : std_logic ;
  signal WDO1_4 : std_logic ;
  signal WDO0_5 : std_logic ;
  signal WDO1_5 : std_logic ;
  signal WDO0_6 : std_logic ;
  signal WDO1_6 : std_logic ;
  signal DATAOUT0_FFIN : std_logic ;
  signal FF_0_QN_0 : std_logic ;
  signal DATAOUT1_FFIN : std_logic ;
  signal FF_1_QN_0 : std_logic ;
  signal DATAOUT2_FFIN : std_logic ;
  signal FF_2_QN_0 : std_logic ;
  signal DATAOUT3_FFIN : std_logic ;
  signal FF_3_QN_0 : std_logic ;
  signal DATAOUT4_FFIN : std_logic ;
  signal FF_4_QN_0 : std_logic ;
  signal DATAOUT5_FFIN : std_logic ;
  signal FF_5_QN_0 : std_logic ;
  signal DATAOUT6_FFIN : std_logic ;
  signal FF_6_QN_0 : std_logic ;
  signal DATAOUT7_FFIN : std_logic ;
  s