uart4.vhm

一个UART的FPGA core

use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity FD1S3DX is
port(
  D :  in std_logic;
  CK :  in std_logic;
  CD :  in std_logic;
  Q :  out std_logic;
  QN :  out std_logic;
  GSR :  in std_logic);
end FD1S3DX;

architecture beh of FD1S3DX is
  signal Q_INT_9 : std_logic ;
  signal GSRN : std_logic ;
  signal CLR : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  GSRN <= not GSR;
  CLR <= CD or GSRN after 100 ps;
  II_ff: prim_dff port map (Q_INT_9, D, CK, CLR, '0');
  QN <= not Q_INT_9;
  GND <= '0';
  VCC <= '1';
  Q <= Q_INT_9;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity FD1S3BX is
port(
  D :  in std_logic;
  CK :  in std_logic;
  PD :  in std_logic;
  Q :  out std_logic;
  QN :  out std_logic;
  GSR :  in std_logic);
end FD1S3BX;

architecture beh of FD1S3BX is
  signal Q_INT_8 : std_logic ;
  signal GSRN : std_logic ;
  signal PRE : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  GSRN <= not GSR;
  PRE <= PD or GSRN after 100 ps;
  II_ff: prim_dff port map (Q_INT_8, D, CK, '0', PRE);
  QN <= not Q_INT_8;
  GND <= '0';
  VCC <= '1';
  Q <= Q_INT_8;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity FD1S3AX is
port(
  D :  in std_logic;
  CK :  in std_logic;
  Q :  out std_logic;
  QN :  out std_logic;
  GSR :  in std_logic);
end FD1S3AX;

architecture beh of FD1S3AX is
  signal Q_INT_10 : std_logic ;
  signal GSRN : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  GSRN <= not GSR;
  II_ff: prim_dff port map (Q_INT_10, D, CK, GSRN, '0');
  QN <= not Q_INT_10;
  GND <= '0';
  VCC <= '1';
  Q <= Q_INT_10;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity FD1P3DX is
port(
  D :  in std_logic;
  SP :  in std_logic;
  CK :  in std_logic;
  CD :  in std_logic;
  Q :  out std_logic;
  QN :  out std_logic;
  GSR :  in std_logic);
end FD1P3DX;

architecture beh of FD1P3DX is
  signal Q_INT_11 : std_logic ;
  signal GSRN : std_logic ;
  signal CLR : std_logic ;
  signal M : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  GSRN <= not GSR;
  CLR <= CD or GSRN after 100 ps;
  M <= Q_INT_11 after 100 ps when SP = '0' else D after 100 ps;
  II_ff: prim_dff port map (Q_INT_11, M, CK, CLR, '0');
  QN <= not Q_INT_11;
  GND <= '0';
  VCC <= '1';
  Q <= Q_INT_11;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity FD1P3BX is
port(
  D :  in std_logic;
  SP :  in std_logic;
  CK :  in std_logic;
  PD :  in std_logic;
  Q :  out std_logic;
  QN :  out std_logic;
  GSR :  in std_logic);
end FD1P3BX;

architecture beh of FD1P3BX is
  signal Q_INT_12 : std_logic ;
  signal GSRN : std_logic ;
  signal PRE : std_logic ;
  signal M : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  GSRN <= not GSR;
  PRE <= PD or GSRN after 100 ps;
  M <= Q_INT_12 after 100 ps when SP = '0' else D after 100 ps;
  II_ff: prim_dff port map (Q_INT_12, M, CK, '0', PRE);
  QN <= not Q_INT_12;
  GND <= '0';
  VCC <= '1';
  Q <= Q_INT_12;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity FD1P3AX is
port(
  D :  in std_logic;
  SP :  in std_logic;
  CK :  in std_logic;
  Q :  out std_logic;
  QN :  out std_logic;
  GSR :  in std_logic);
end FD1P3AX;

architecture beh of FD1P3AX is
  signal Q_INT_0 : std_logic ;
  signal GSRN : std_logic ;
  signal M : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  GSRN <= not GSR;
  M <= Q_INT_0 after 100 ps when SP = '0' else D after 100 ps;
  II_ff: prim_dff port map (Q_INT_0, M, CK, GSRN, '0');
  QN <= not Q_INT_0;
  GND <= '0';
  VCC <= '1';
  Q <= Q_INT_0;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity AND2 is
port(
  A :  in std_logic;
  B :  in std_logic;
  Z :  out std_logic);
end AND2;

architecture beh of AND2 is
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  Z <= B and A after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity L6MUX21 is
port(
  D1 :  in std_logic;
  D0 :  in std_logic;
  SD :  in std_logic;
  Z :  out std_logic);
end L6MUX21;

architecture beh of L6MUX21 is
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  Z <= D0 after 100 ps when SD = '0' else D1 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity PFUMX is
port(
  ALUT :  in std_logic;
  BLUT :  in std_logic;
  C0 :  in std_logic;
  Z :  out std_logic);
end PFUMX;

architecture beh of PFUMX is
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  Z <= BLUT after 100 ps when C0 = '0' else ALUT after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity INV is
port(
  A :  in std_logic;
  Z :  out std_logic);
end INV;

architecture beh of INV is
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  Z <= not A;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity VHI is
port(
  Z :  out std_logic);
end VHI;

architecture beh of VHI is
  signal GND : std_logic ;
begin
  Z <= '1';
  GND <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity VLO is
port(
  Z :  out std_logic);
end VLO;

architecture beh of VLO is
  signal VCC : std_logic ;
begin
  Z <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity dpram16x8_7_1 is
port(
  datar_out3 : out std_logic_vector (7 downto 0);
  rsr : in std_logic_vector (7 downto 0);
  top_i : in std_logic_vector (0 downto 0);
  bottom : in std_logic_vector (3 downto 0);
  wr :  in std_logic;
  VCC :  in std_logic;
  rst_c :  in std_logic;
  pop :  in std_logic;
  GND :  in std_logic;
  clk_c :  in std_logic;
  un1_top_axbxc3_6 :  in std_logic;
  un1_top_axbxc2_6 :  in std_logic;
  un1_top_axbxc1_6 :  in std_logic);
end dpram16x8_7_1;

architecture beh of dpram16x8_7_1 is
  signal WDO0_27 : std_logic ;
  signal WDO1_27 : std_logic ;
  signal WDO0_28 : std_logic ;
  signal WDO1_28 : std_logic ;
  signal WDO0_29 : std_logic ;
  signal WDO1_29 : std_logic ;
  signal WDO0_30 : std_logic ;
  signal WDO1_30 : std_logic ;
  signal DATAOUT0_FFIN : std_logic ;
  signal FF_0_QN_6 : std_logic ;
  signal DATAOUT1_FFIN : std_logic ;
  signal FF_1_QN_6 : std_logic ;
  signal DATAOUT2_FFIN : std_logic ;
  signal FF_2_QN_6 : std_logic ;
  signal DATAOUT3_FFIN : std_logic ;
  signal FF_3_QN_6 : std_logic ;
  signal DATAOUT4_FFIN : std_logic ;
  signal FF_4_QN_6 : std_logic ;
  signal DATAOUT5_FFIN : std_logic ;
  signal FF_5_QN_6 : std_logic ;
  signal DATAOUT6_FFIN : std_logic ;
  signal FF_6_QN_6 : std_logic ;
  signal DATAOUT7_FFIN : std_logic ;
  signal FF_7_QN_6 : std_logic ;
  signal DEC_WRE3 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  component DPR16X2B
    port(
      RDO0 : out std_logic;
      RDO1 : out std_logic;
      WDO0 : out std_logic;
      WDO1 : out std_logic;
      RAD0 : in std_logic;
      RAD1 : in std_logic;
      RAD2 : in std_logic;
      RAD3 : in std_logic;
      WAD0 : in std_logic;
      WAD1 : in std_logic;
      WAD2 : in std_logic;
      WAD3 : in std_logic;
      DI0 : in std_logic;
      DI1 : in std_logic;
      WRE : in std_logic;
      WCK : in std_logic;
      GSR : in std_logic  );
  end component;
  component FD1P3DX
    port(
      D : in std_logic;
      SP : in std_logic;
      CK : in std_logic;
      CD : in std_logic;
      Q : out std_logic;
      QN : out std_logic;
      GSR : in std_logic  );
  end component;
  component AND2
    port(
      A : in std_logic;
      B : in std_logic;
      Z : out std_logic  );
  end component;
begin
  II_mem_0_3: DPR16X2B port map (
      RDO0 => DATAOUT0_FFIN,
      RDO1 => DATAOUT1_FFIN,
      WDO0 => WDO0_27,
      WDO1 => WDO1_27,
      RAD0 => bottom(0),
      RAD1 => bottom(1),
      RAD2 => bottom(2),
      RAD3 => bottom(3),
      WAD0 => top_i(0),
      WAD1 => un1_top_axbxc1_6,
      WAD2 => un1_top_axbxc2_6,
      WAD3 => un1_top_axbxc3_6,
      DI0 => rsr(0),
      DI1 => rsr(1),
      WRE => DEC_WRE3,
      WCK => clk_c,
      GSR => GND);
  II_mem_0_2: DPR16X2B port map (
      RDO0 => DATAOUT2_FFIN,
      RDO1 => DATAOUT3_FFIN,
      WDO0 => WDO0_28,
      WDO1 => WDO1_28,
      RAD0 => bottom(0),
      RAD1 => bottom(1),
      RAD2 => bottom(2),