uart.tw1

一个UART的FPGA core

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Lattice TRACE Report, Version ispLever_v51_SP2_Build (10)
Fri Jul 07 14:17:01 2006

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2006 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
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Command line:    trce -v 1 -gt -o checkpnt.twr uart_map.ncd uart.prf 
Design file:     uart_map.ncd
Preference file: uart.prf
Device,speed:    LCMXO640C,3
Report level:    verbose report, limited to 1 item per preference
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BLOCK ASYNCPATHS
BLOCK RESETPATHS
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================================================================================
Preference: FREQUENCY PORT "clk" 50.000000 MHz ;
            2773 items scored, 0 timing errors detected.
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Passed:  The following path meets requirements by 7.722ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FF         Q              u12/intmask_2__Q  (from clk_c -)
   Destination:    FF         Data in        u12/int_reg_Q  (to clk_c +)

   Delay:               2.097ns  (100.0% logic, 0.0% route), 5 logic levels.

 Constraint Details:

       2.097ns physical path delay SLICE_283 to u12/SLICE_122 meets
      10.000ns delay constraint less
       0.181ns DIN_SET requirement (totaling 9.819ns) by 7.722ns

 Physical Path Details:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.613  SLICE_283.CLK to   SLICE_283.Q0 SLICE_283 (from clk_c)
ROUTE         1   e 0.000   SLICE_283.Q0 to   SLICE_287.C1 u12/intmask_2
CTOF_DEL    ---     0.371   SLICE_287.C1 to   SLICE_287.F1 SLICE_287
ROUTE         1   e 0.000   SLICE_287.F1 to   SLICE_287.C0 u12/fifot2_intZ0
CTOF_DEL    ---     0.371   SLICE_287.C0 to   SLICE_287.F0 SLICE_287
ROUTE         1   e 0.000   SLICE_287.F0 to 2/SLICE_122.D1 u12/int_regsrZ0Z_2
CTOF_DEL    ---     0.371 2/SLICE_122.D1 to 2/SLICE_122.F1 u12/SLICE_122
ROUTE         1   e 0.000 2/SLICE_122.F1 to 2/SLICE_122.A0 u12/int_regs_iZ0
CTOF_DEL    ---     0.371 2/SLICE_122.A0 to 2/SLICE_122.F0 u12/SLICE_122
ROUTE         1   e 0.000 2/SLICE_122.F0 to /SLICE_122.DI0 u12/Q_0 (to clk_c)
                  --------
                    2.097   (100.0% logic, 0.0% route), 5 logic levels.

Report:  219.491MHz is the maximum frequency for this preference.

Report Summary
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----------------------------------------------------------------------------
Preference                              |   Constraint|       Actual|Levels
----------------------------------------------------------------------------
                                        |             |             |
FREQUENCY PORT "clk" 50.000000 MHz ;    |   50.000 MHz|  219.491 MHz|     5
                                        |             |             |
----------------------------------------------------------------------------


All preferences were met.


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 2773 paths, 1 nets, and 1657 connections (58.7% coverage)

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