deccounter.tan.rpt

基于VHDL的4位带异步清零的二进制计数器。

; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CNT4B:inst5|CQI[0] ; CNT4B:inst5|CQI[2] ; CLK        ; CLK      ; None                        ; None                      ; 0.901 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CNT4B:inst5|CQI[0] ; CNT4B:inst5|CQI[1] ; CLK        ; CLK      ; None                        ; None                      ; 0.895 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CNT4B:inst5|CQI[0] ; CNT4B:inst5|CQI[0] ; CLK        ; CLK      ; None                        ; None                      ; 0.889 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CNT4B:inst|CQI[2]  ; CNT4B:inst|CQI[3]  ; CLK        ; CLK      ; None                        ; None                      ; 1.121 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CNT4B:inst|CQI[1]  ; CNT4B:inst|CQI[2]  ; CLK        ; CLK      ; None                        ; None                      ; 1.078 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CNT4B:inst|CQI[1]  ; CNT4B:inst|CQI[1]  ; CLK        ; CLK      ; None                        ; None                      ; 1.075 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CNT4B:inst|CQI[0]  ; CNT4B:inst|CQI[0]  ; CLK        ; CLK      ; None                        ; None                      ; 1.075 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CNT4B:inst|CQI[1]  ; CNT4B:inst|CQI[3]  ; CLK        ; CLK      ; None                        ; None                      ; 1.073 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CNT4B:inst|CQI[2]  ; CNT4B:inst|CQI[2]  ; CLK        ; CLK      ; None                        ; None                      ; 0.837 ns                ;
+-------+------------------------------------------------+--------------------+--------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+--------------------------------------------------------------------------------+
; tco                                                                            ;
+-------+--------------+------------+---------------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From                ; To      ; From Clock ;
+-------+--------------+------------+---------------------+---------+------------+
; N/A   ; None         ; 14.219 ns  ; REG4B:inst2|DOUT[3] ; OUT1[3] ; CLKK       ;
; N/A   ; None         ; 13.560 ns  ; REG4B:inst3|DOUT[1] ; OUT2[1] ; CLKK       ;
; N/A   ; None         ; 12.890 ns  ; REG4B:inst3|DOUT[2] ; OUT2[2] ; CLKK       ;
; N/A   ; None         ; 12.887 ns  ; REG4B:inst4|DOUT[3] ; OUT3[3] ; CLKK       ;
; N/A   ; None         ; 12.819 ns  ; REG4B:inst2|DOUT[0] ; OUT1[0] ; CLKK       ;
; N/A   ; None         ; 12.556 ns  ; REG4B:inst3|DOUT[0] ; OUT2[0] ; CLKK       ;
; N/A   ; None         ; 12.540 ns  ; REG4B:inst4|DOUT[0] ; OUT3[0] ; CLKK       ;
; N/A   ; None         ; 12.365 ns  ; REG4B:inst1|DOUT[1] ; OUT0[1] ; CLKK       ;
; N/A   ; None         ; 12.347 ns  ; REG4B:inst1|DOUT[2] ; OUT0[2] ; CLKK       ;
; N/A   ; None         ; 12.287 ns  ; REG4B:inst1|DOUT[0] ; OUT0[0] ; CLKK       ;
; N/A   ; None         ; 12.126 ns  ; REG4B:inst3|DOUT[3] ; OUT2[3] ; CLKK       ;
; N/A   ; None         ; 12.029 ns  ; REG4B:inst4|DOUT[2] ; OUT3[2] ; CLKK       ;
; N/A   ; None         ; 11.839 ns  ; REG4B:inst4|DOUT[1] ; OUT3[1] ; CLKK       ;
; N/A   ; None         ; 11.839 ns  ; REG4B:inst2|DOUT[1] ; OUT1[1] ; CLKK       ;
; N/A   ; None         ; 11.839 ns  ; REG4B:inst1|DOUT[3] ; OUT0[3] ; CLKK       ;
; N/A   ; None         ; 11.801 ns  ; REG4B:inst2|DOUT[2] ; OUT1[2] ; CLKK       ;
+-------+--------------+------------+---------------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Sat Dec 08 16:04:02 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off deccounter -c deccounter --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLKK" is an undefined clock
    Info: Assuming node "CLK" is an undefined clock
Warning: Found 10 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "CNT4B:inst6|COUT" as buffer
    Info: Detected gated clock "CNT4B:inst5|COUT" as buffer
    Info: Detected gated clock "CNT4B:inst|COUT" as buffer
    Info: Detected ripple clock "CNT4B:inst6|CQI[0]" as buffer
    Info: Detected ripple clock "CNT4B:inst6|CQI[3]" as buffer
    Info: Detected ripple clock "CNT4B:inst5|CQI[0]" as buffer
    Info: Detected ripple clock "CNT4B:inst5|CQI[3]" as buffer
    Info: Detected ripple clock "CNT4B:inst|CQI[0]" as buffer
    Info: Detected ripple clock "TESTCTL:inst8|DIV2CLK" as buffer
    Info: Detected ripple clock "CNT4B:inst|CQI[3]" as buffer
Info: Clock "CLKK" Internal fmax is restricted to 275.03 MHz between source register "TESTCTL:inst8|DIV2CLK" and destination register "TESTCTL:inst8|DIV2CLK"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.822 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y6_N0; Fanout = 37; REG Node = 'TESTCTL:inst8|DIV2CLK'
            Info: 2: + IC(0.513 ns) + CELL(0.309 ns) = 0.822 ns; Loc. = LC_X8_Y6_N0; Fanout = 37; REG Node = 'TESTCTL:inst8|DIV2CLK'
            Info: Total cell delay = 0.309 ns ( 37.59 % )
            Info: Total interconnect delay = 0.513 ns ( 62.41 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLKK" to destination register is 3.903 ns
                Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_47; Fanout = 5; CLK Node = 'CLKK'
                Info: 2: + IC(1.717 ns) + CELL(0.711 ns) = 3.903 ns; Loc. = LC_X8_Y6_N0; Fanout = 37; REG Node = 'TESTCTL:inst8|DIV2CLK'
                Info: Total cell delay = 2.186 ns ( 56.01 % )
                Info: Total interconnect delay = 1.717 ns ( 43.99 % )
            Info: - Longest clock path from clock "CLKK" to source register is 3.903 ns
                Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_47; Fanout = 5; CLK Node = 'CLKK'
                Info: 2: + IC(1.717 ns) + CELL(0.711 ns) = 3.903 ns; Loc. = LC_X8_Y6_N0; Fanout = 37; REG Node = 'TESTCTL:inst8|DIV2CLK'
                Info: Total cell delay = 2.186 ns ( 56.01 % )
                Info: Total interconnect delay = 1.717 ns ( 43.99 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: Clock "CLK" Internal fmax is restricted to 275.03 MHz between source register "CNT4B:inst7|CQI[3]" and destination register "CNT4B:inst7|CQI[3]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.260 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y8_N2; Fanout = 3; REG Node = 'CNT4B:inst7|CQI[3]'
            Info: 2: + IC(0.522 ns) + CELL(0.738 ns) = 1.260 ns; Loc. = LC_X23_Y8_N2; Fanout = 3; REG Node = 'CNT4B:inst7|CQI[3]'
            Info: Total cell delay = 0.738 ns ( 58.57 % )
            Info: Total interconnect delay = 0.522 ns ( 41.43 % )
        Info: - Smallest clock skew is -0.540 ns
            Info: + Shortest clock path from clock "CLK" to destination register is 20.104 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 4; CLK Node = 'CLK'
                Info: 2: + IC(0.602 ns) + CELL(0.935 ns) = 3.006 ns; Loc. = LC_X26_Y7_N6; Fanout = 4; REG Node = 'CNT4B:inst|CQI[3]'
                Info: 3: + IC(0.536 ns) + CELL(0.114 ns) = 3.656 ns; Loc. = LC_X26_Y7_N4; Fanout = 4; COMB Node = 'CNT4B:inst|COUT'
                Info: 4: + IC(4.374 ns) + CELL(0.935 ns) = 8.965 ns; Loc. = LC_X26_Y6_N6; Fanout = 7; REG Node = 'CNT4B:inst5|CQI[0]'
                Info: 5: + IC(0.582 ns) + CELL(0.114 ns) = 9.661 ns; Loc. = LC_X26_Y6_N5; Fanout = 4; COMB Node = 'CNT4B:inst5|COUT'
                Info: 6: + IC(3.650 ns) + CELL(0.935 ns) = 14.246 ns; Loc. = LC_X23_Y7_N0; Fanout = 7; REG Node = 'CNT4B:inst6|CQI[0]'
                Info: 7: + IC(0.612 ns) + CELL(0.114 ns) = 14.972 ns; Loc. = LC_X23_Y7_N6; Fanout = 4; COMB Node = 'CNT4B:inst6|COUT'
                Info: 8: + IC(4.421 ns) + CELL(0.711 ns) = 20.104 ns; Loc. = LC_X23_Y8_N2; Fanout = 3; REG Node = 'CNT4B:inst7|CQI[3]'
                Info: Total cell delay = 5.327 ns ( 26.50 % )
                Info: Total interconnect delay = 14.777 ns ( 73.50 % )
            Info: - Longest clock path from clock "CLK" to source register is 20.644 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 4; CLK Node = 'CLK'
                Info: 2: + IC(0.602 ns) + CELL(0.935 ns) = 3.006 ns; Loc. = LC_X26_Y7_N9; Fanout = 7; REG Node = 'CNT4B:inst|CQI[0]'
                Info: 3: + IC(0.597 ns) + CELL(0.292 ns) = 3.895 ns; Loc. = LC_X26_Y7_N4; Fanout = 4; COMB Node = 'CNT4B:inst|COUT'
                Info: 4: + IC(4.374 ns) + CELL(0.935 ns) = 9.204 ns; Loc. = LC_X26_Y6_N2; Fanout = 4; REG Node = 'CNT4B:inst5|CQI[3]'
                Info: 5: + IC(0.567 ns) + CELL(0.292 ns) = 10.063 ns; Loc. = LC_X26_Y6_N5; Fanout = 4; COMB Node = 'CNT4B:inst5|COUT'
                Info: 6: + IC(3.650 ns) + CELL(0.935 ns) = 14.648 ns; Loc. = LC_X23_Y7_N2; Fanout = 4; REG Node = 'CNT4B:inst6|CQI[3]'
                Info: 7: + IC(0.572 ns) + CELL(0.292 ns) = 15.512 ns; Loc. = LC_X23_Y7_N6; Fanout = 4; COMB Node = 'CNT4B:inst6|COUT'
                Info: 8: + IC(4.421 ns) + CELL(0.711 ns) = 20.644 ns; Loc. = LC_X23_Y8_N2; Fanout = 3; REG Node = 'CNT4B:inst7|CQI[3]'
                Info: Total cell delay = 5.861 ns ( 28.39 % )
                Info: Total interconnect delay = 14.783 ns ( 71.61 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "CLKK" to destination pin "OUT1[3]" through register "REG4B:inst2|DOUT[3]" is 14.219 ns
    Info: + Longest clock path from clock "CLKK" to source register is 8.350 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_47; Fanout = 5; CLK Node = 'CLKK'
        Info: 2: + IC(1.717 ns) + CELL(0.935 ns) = 4.127 ns; Loc. = LC_X8_Y6_N0; Fanout = 37; REG Node = 'TESTCTL:inst8|DIV2CLK'
        Info: 3: + IC(3.512 ns) + CELL(0.711 ns) = 8.350 ns; Loc. = LC_X26_Y9_N2; Fanout = 1; REG Node = 'REG4B:inst2|DOUT[3]'
        Info: Total cell delay = 3.121 ns ( 37.38 % )
        Info: Total interconnect delay = 5.229 ns ( 62.62 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 5.645 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y9_N2; Fanout = 1; REG Node = 'REG4B:inst2|DOUT[3]'
        Info: 2: + IC(3.521 ns) + CELL(2.124 ns) = 5.645 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'OUT1[3]'
        Info: Total cell delay = 2.124 ns ( 37.63 % )
        Info: Total interconnect delay = 3.521 ns ( 62.37 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Allocated 106 megabytes of memory during processing
    Info: Processing ended: Sat Dec 08 16:04:03 2007
    Info: Elapsed time: 00:00:01