deccounter.fnsim.qmsg

基于VHDL的4位带异步清零的二进制计数器。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 08 16:11:49 2007 " "Info: Processing started: Sat Dec 08 16:11:49 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off deccounter -c deccounter --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off deccounter -c deccounter --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CNT4B.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file CNT4B.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CNT4B-behav " "Info: Found design unit 1: CNT4B-behav" {  } { { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 CNT4B " "Info: Found entity 1: CNT4B" {  } { { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "TESTCTL.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file TESTCTL.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 TESTCTL-behav " "Info: Found design unit 1: TESTCTL-behav" {  } { { "TESTCTL.vhd" "" { Text "E:/EDA/实验六/TESTCTL.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 TESTCTL " "Info: Found entity 1: TESTCTL" {  } { { "TESTCTL.vhd" "" { Text "E:/EDA/实验六/TESTCTL.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "REG4B.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file REG4B.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 REG4B-behav " "Info: Found design unit 1: REG4B-behav" {  } { { "REG4B.vhd" "" { Text "E:/EDA/实验六/REG4B.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 REG4B " "Info: Found entity 1: REG4B" {  } { { "REG4B.vhd" "" { Text "E:/EDA/实验六/REG4B.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "deccounter.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file deccounter.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 deccounter " "Info: Found entity 1: deccounter" {  } { { "deccounter.bdf" "" { Schematic "E:/EDA/实验六/deccounter.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "deccounter " "Info: Elaborating entity \"deccounter\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "REG4B REG4B:inst1 " "Info: Elaborating entity \"REG4B\" for hierarchy \"REG4B:inst1\"" {  } { { "deccounter.bdf" "inst1" { Schematic "E:/EDA/实验六/deccounter.bdf" { { 48 536 696 144 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "TESTCTL TESTCTL:inst8 " "Info: Elaborating entity \"TESTCTL\" for hierarchy \"TESTCTL:inst8\"" {  } { { "deccounter.bdf" "inst8" { Schematic "E:/EDA/实验六/deccounter.bdf" { { 64 80 208 160 "inst8" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CNT4B CNT4B:inst " "Info: Elaborating entity \"CNT4B\" for hierarchy \"CNT4B:inst\"" {  } { { "deccounter.bdf" "inst" { Schematic "E:/EDA/实验六/deccounter.bdf" { { 64 312 448 160 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CQI CNT4B.vhd(21) " "Warning (10492): VHDL Process Statement warning at CNT4B.vhd(21): signal \"CQI\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 21 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CQI CNT4B.vhd(22) " "Warning (10492): VHDL Process Statement warning at CNT4B.vhd(22): signal \"CQI\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 22 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CQI CNT4B.vhd(23) " "Warning (10492): VHDL Process Statement warning at CNT4B.vhd(23): signal \"CQI\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 23 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../quartus/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../quartus/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "e:/eda/quartus/libraries/megafunctions/lpm_add_sub.tdf" 102 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "CNT4B:inst7\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"CNT4B:inst7\|lpm_add_sub:Add0\"" {  } { { "e:/eda/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/eda/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}