prev_cmp_deccounter.map.qmsg

基于VHDL的4位带异步清零的二进制计数器。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 25 13:56:52 2007 " "Info: Processing started: Tue Dec 25 13:56:52 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off deccounter -c deccounter " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off deccounter -c deccounter" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "C:/Documents and Settings/Administrator/桌面/TEST.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file C:/Documents and Settings/Administrator/桌面/TEST.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 TEST-behav " "Info: Found design unit 1: TEST-behav" {  } { { "C:/Documents and Settings/Administrator/桌面/TEST.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/TEST.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 TEST " "Info: Found entity 1: TEST" {  } { { "C:/Documents and Settings/Administrator/桌面/TEST.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/TEST.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CNT4B.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file CNT4B.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CNT4B-behav " "Info: Found design unit 1: CNT4B-behav" {  } { { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 CNT4B " "Info: Found entity 1: CNT4B" {  } { { "CNT4B.vhd" "" { Text "E:/EDA/实验六/CNT4B.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "TESTCTL.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file TESTCTL.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 TESTCTL-behav " "Info: Found design unit 1: TESTCTL-behav" {  } { { "TESTCTL.vhd" "" { Text "E:/EDA/实验六/TESTCTL.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 TESTCTL " "Info: Found entity 1: TESTCTL" {  } { { "TESTCTL.vhd" "" { Text "E:/EDA/实验六/TESTCTL.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "REG4B.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file REG4B.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 REG4B-behav " "Info: Found design unit 1: REG4B-behav" {  } { { "REG4B.vhd" "" { Text "E:/EDA/实验六/REG4B.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 REG4B " "Info: Found entity 1: REG4B" {  } { { "REG4B.vhd" "" { Text "E:/EDA/实验六/REG4B.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "deccounter.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file deccounter.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 deccounter " "Info: Found entity 1: deccounter" {  } { { "deccounter.bdf" "" { Schematic "E:/EDA/实验六/deccounter.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "TEST " "Info: Elaborating entity \"TEST\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CQI TEST.vhd(35) " "Warning (10492): VHDL Process Statement warning at TEST.vhd(35): signal \"CQI\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "C:/Documents and Settings/Administrator/桌面/TEST.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/TEST.vhd" 35 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CQI TEST.vhd(36) " "Warning (10492): VHDL Process Statement warning at TEST.vhd(36): signal \"CQI\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "C:/Documents and Settings/Administrator/桌面/TEST.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/TEST.vhd" 36 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "15 " "Info: Implemented 15 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "5 " "Info: Implemented 5 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Info: Implemented 8 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "152 " "Info: Allocated 152 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 25 13:56:56 2007 " "Info: Processing ended: Tue Dec 25 13:56:56 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}