clkgen.hif

用最少的CPLD资源,用Verilog在QuartusII7.1上实现的1280分频.

Version 7.1 Build 156 04/30/2007 SJ Full Version
37
2171
OFF
OFF
OFF
OFF
ON
ON
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
lpm_divide
# storage
db|clkgen.(1).cnf
db|clkgen.(1).cnf
# case_insensitive
# source_file
d:|altera71|quartus|libraries|megafunctions|lpm_divide.tdf
a85dc8b71537a0c1b2c5a9ae304069d7
6
# user_parameter {
LPM_WIDTHN
3
PARAMETER_UNKNOWN
USR
LPM_WIDTHD
3
PARAMETER_UNKNOWN
USR
LPM_NREPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_DREPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
LPM_REMAINDERPOSITIVE
TRUE
PARAMETER_UNKNOWN
DEF
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
lpm_divide_nnl
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
remain2
-1
3
remain1
-1
3
remain0
-1
3
numer2
-1
3
numer1
-1
3
numer0
-1
3
denom1
-1
1
denom2
-1
2
denom0
-1
2
}
# include_file {
d:|altera71|quartus|libraries|megafunctions|sign_div_unsign.inc
c1e17922387cb5d0c88d7fb673544bb4
d:|altera71|quartus|libraries|megafunctions|abs_divider.inc
cdfefd53e136b3a8e541899b82db37d
d:|altera71|quartus|libraries|megafunctions|aglobal71.inc
80b63f71158cd1a01acf29ef94ccd6
}
# lmf
d:|altera71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
lpm_divide_nnl
# storage
db|clkgen.(2).cnf
db|clkgen.(2).cnf
# case_insensitive
# source_file
db|lpm_divide_nnl.tdf
9d52b2e1dbfbc7a8112314f1ba31d585
6
# used_port {
remain2
-1
3
remain1
-1
3
remain0
-1
3
numer2
-1
3
numer1
-1
3
numer0
-1
3
denom2
-1
3
denom1
-1
3
denom0
-1
3
}
# lmf
d:|altera71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
sign_div_unsign_5kh
# storage
db|clkgen.(3).cnf
db|clkgen.(3).cnf
# case_insensitive
# source_file
db|sign_div_unsign_5kh.tdf
994c6c9d8fb7b0ff2e7d964ca1dc2cd2
6
# used_port {
remainder2
-1
3
remainder1
-1
3
remainder0
-1
3
quotient2
-1
3
quotient1
-1
3
quotient0
-1
3
numerator2
-1
3
numerator1
-1
3
numerator0
-1
3
denominator2
-1
3
denominator1
-1
3
denominator0
-1
3
}
# lmf
d:|altera71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
alt_u_div_5ie
# storage
db|clkgen.(4).cnf
db|clkgen.(4).cnf
# case_insensitive
# source_file
db|alt_u_div_5ie.tdf
8ee953ecaabab7451e31afaaf17b7da2
6
# used_port {
remainder2
-1
3
remainder1
-1
3
remainder0
-1
3
quotient2
-1
3
quotient1
-1
3
quotient0
-1
3
numerator2
-1
3
numerator1
-1
3
numerator0
-1
3
denominator2
-1
3
denominator1
-1
3
denominator0
-1
3
}
# lmf
d:|altera71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
add_sub_e7c
# storage
db|clkgen.(5).cnf
db|clkgen.(5).cnf
# case_insensitive
# source_file
db|add_sub_e7c.tdf
34b2c2062106ad1562b9cae5ff3161
6
# used_port {
result0
-1
3
datab0
-1
3
dataa0
-1
3
cout
-1
3
}
# lmf
d:|altera71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
add_sub_f7c
# storage
db|clkgen.(6).cnf
db|clkgen.(6).cnf
# case_insensitive
# source_file
db|add_sub_f7c.tdf
77dfeb1fcdffc8ca620526938f6885f
6
# used_port {
result1
-1
3
result0
-1
3
datab1
-1
3
datab0
-1
3
dataa1
-1
3
dataa0
-1
3
cout
-1
3
}
# lmf
d:|altera71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
add_sub_g7c
# storage
db|clkgen.(7).cnf
db|clkgen.(7).cnf
# case_insensitive
# source_file
db|add_sub_g7c.tdf
9a9b57ab6eb6793cec25b8f99503a
6
# used_port {
result2
-1
3
result1
-1
3
result0
-1
3
datab2
-1
3
datab1
-1
3
datab0
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
cout
-1
3
}
# lmf
d:|altera71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
add_sub_f3c
# storage
db|clkgen.(8).cnf
db|clkgen.(8).cnf
# case_insensitive
# source_file
db|add_sub_f3c.tdf
c49a82f39ba83e223ed8176cf79bc2ca
6
# used_port {
datab2
-1
3
datab1
-1
3
datab0
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
cin
-1
3
}
# lmf
d:|altera71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
clkgen
# storage
db|clkgen.(0).cnf
db|clkgen.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
clkgen.v
af4497cc1e4b645efd95ad91c25d8ff
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
|
}
# lmf
d:|altera71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# complete