clkgen.tan.summary

来自「用最少的CPLD资源,用Verilog在QuartusII7.1上实现的1280」· SUMMARY 代码 · 共 37 行

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Timing Analyzer Summary
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Type           : Clock Setup: 'CLKin'
Slack          : 95.877 ns
Required Time  : 10.24 MHz ( period = 97.656 ns )
Actual Time    : Restricted to 304.04 MHz ( period = 3.289 ns )
From           : i[2]
To             : i[0]
From Clock     : CLKin
To Clock       : CLKin
Failed Paths   : 0

Type           : Clock Hold: 'CLKin'
Slack          : 1.024 ns
Required Time  : 10.24 MHz ( period = 97.656 ns )
Actual Time    : N/A
From           : clk_div8
To             : clk_div8
From Clock     : CLKin
To Clock       : CLKin
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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