clkgen.sim.qrpt
来自「用最少的CPLD资源,用Verilog在QuartusII7.1上实现的1280」· QRPT 代码 · 共 59 行
QRPT
59 行
[PAGE_SETUP]
BOTTOM_MARGIN=1.000000
CENTER_FOOTER=Page %p of %P
CENTER_HEADER=%f
LEFT_FOOTER=Prepared by Chong-Ming WEI
LEFT_HEADER=Date: %D
LEFT_MARGIN=1.000000
PAPER_SIZE=133
PAPER_SOURCE=15
RIGHT_FOOTER=Revision: %a
RIGHT_HEADER=Project: %j
RIGHT_MARGIN=1.000000
TOP_MARGIN=1.000000
[||Simulation Report]
OUTPUT_SECTION=1
PAGE_ORIENTATION=0
[||Simulation Report||Flow Settings]
OUTPUT_SECTION=1
PAGE_ORIENTATION=0
[||Simulation Report||Flow Summary]
OUTPUT_SECTION=1
PAGE_ORIENTATION=0
[||Simulation Report||Legal Notice]
OUTPUT_SECTION=1
PAGE_ORIENTATION=0
[||Simulation Report||Simulator]
OUTPUT_SECTION=1
PAGE_ORIENTATION=0
[||Simulation Report||Simulator||Simulation Coverage]
OUTPUT_SECTION=1
PAGE_ORIENTATION=0
[||Simulation Report||Simulator||Simulation Coverage||Complete 1/0-Value Coverage]
OUTPUT_SECTION=1
PAGE_ORIENTATION=0
[||Simulation Report||Simulator||Simulation Coverage||Coverage Summary]
OUTPUT_SECTION=1
PAGE_ORIENTATION=0
[||Simulation Report||Simulator||Simulation Coverage||Missing 0-Value Coverage]
OUTPUT_SECTION=1
PAGE_ORIENTATION=0
[||Simulation Report||Simulator||Simulation Coverage||Missing 1-Value Coverage]
OUTPUT_SECTION=1
PAGE_ORIENTATION=0
[||Simulation Report||Simulator||Simulation Waveforms]
OUTPUT_SECTION=1
PAGE_ORIENTATION=1
[||Simulation Report||Simulator||Simulator INI Usage]
OUTPUT_SECTION=1
PAGE_ORIENTATION=0
[||Simulation Report||Simulator||Simulator Messages]
OUTPUT_SECTION=1
PAGE_ORIENTATION=0
[||Simulation Report||Simulator||Simulator Settings]
OUTPUT_SECTION=1
PAGE_ORIENTATION=0
[||Simulation Report||Simulator||Simulator Summary]
OUTPUT_SECTION=1
PAGE_ORIENTATION=0
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