clkgen.qsf

用最少的CPLD资源,用Verilog在QuartusII7.1上实现的1280分频.

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		clkgen_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name DEVICE EPM1270T144C3
set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name TOP_LEVEL_ENTITY clkgen
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:10:38  NOVEMBER 17, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 7.1
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 3
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name VERILOG_FILE clkgen.v
set_global_assignment -name VECTOR_WAVEFORM_FILE clkgen.vwf
set_global_assignment -name FMAX_REQUIREMENT "300 MHz"
set_global_assignment -name SMART_RECOMPILE OFF
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF
set_global_assignment -name FMAX_REQUIREMENT "10.24 MHz" -section_id CLKin
set_instance_assignment -name CLOCK_SETTINGS CLKin -to CLKin
set_global_assignment -name BASED_ON_CLOCK_SETTINGS CLKin -section_id CLKout
set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 1280 -section_id CLKout
set_global_assignment -name OFFSET_FROM_BASE_CLOCK "10 ns" -section_id CLKout
set_instance_assignment -name CLOCK_SETTINGS CLKout -to CLKout
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE OPTIMISTIC
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE BALANCED
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
set_global_assignment -name MUX_RESTRUCTURE OFF
set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES ON
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_GATE_RETIME OFF
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "1 ns"
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT ON
set_instance_assignment -name TSU_REQUIREMENT "6 ns" -from * -to *
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE clkgen.vwf