clkgen.map.summary

来自「用最少的CPLD资源,用Verilog在QuartusII7.1上实现的1280」· SUMMARY 代码 · 共 10 行

Analysis & Synthesis Status : Successful - Sat Nov 17 21:16:15 2007
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version
Revision Name : clkgen
Top-level Entity Name : clkgen
Family : MAX II
Total logic elements : 11
Total pins : 2
Total virtual pins : 0
UFM blocks : 0