clkgen.fit.rpt

用最少的CPLD资源,用Verilog在QuartusII7.1上实现的1280分频.

; Reserve all unused pins                      ; As input tri-stated ;
; Base pin-out file on sameframe device        ; Off                 ;
+----------------------------------------------+---------------------+


+----------------------------+
; Advanced Data - General    ;
+--------------------+-------+
; Name               ; Value ;
+--------------------+-------+
; Status Code        ; 1000  ;
; Desired User Slack ; 0     ;
; Fit Attempts       ; 1     ;
+--------------------+-------+


+------------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                                    ;
+--------------------------------------------------------------------------------+---------+
; Name                                                                           ; Value   ;
+--------------------------------------------------------------------------------+---------+
; Auto Fit Point 1 - Fit Attempt 1                                               ; ff      ;
; Mid Wire Use - Fit Attempt 1                                                   ; 0       ;
; Mid Slack - Fit Attempt 1                                                      ; 92672   ;
; Internal Atom Count - Fit Attempt 1                                            ; 11      ;
; LE/ALM Count - Fit Attempt 1                                                   ; 11      ;
; LAB Count - Fit Attempt 1                                                      ; 4       ;
; Outputs per Lab - Fit Attempt 1                                                ; 1.000   ;
; Inputs per LAB - Fit Attempt 1                                                 ; 0.750   ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 0.250   ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 1:1;2:3 ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:4     ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 1:1;2:3 ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:4     ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 1:1;2:3 ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:4     ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:4     ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:4     ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 1:4     ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:3;1:1 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 2:4     ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:4     ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 1:4     ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:4     ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 0:3;1:1 ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:4     ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:4     ;
; LEs in Chains - Fit Attempt 1                                                  ; 0       ;
; LEs in Long Chains - Fit Attempt 1                                             ; 0       ;
; LABs with Chains - Fit Attempt 1                                               ; 0       ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0       ;
; Time - Fit Attempt 1                                                           ; 0       ;
+--------------------------------------------------------------------------------+---------+


+----------------------------------------------+
; Advanced Data - Placement                    ;
+--------------------------------------+-------+
; Name                                 ; Value ;
+--------------------------------------+-------+
; Auto Fit Point 2 - Fit Attempt 1     ; ff    ;
; Early Wire Use - Fit Attempt 1       ; 0     ;
; Early Slack - Fit Attempt 1          ; 93870 ;
; Auto Fit Point 4 - Fit Attempt 1     ; ff    ;
; Auto Fit Point 5 - Fit Attempt 1     ; ff    ;
; Mid Wire Use - Fit Attempt 1         ; 0     ;
; Mid Slack - Fit Attempt 1            ; 93870 ;
; Auto Fit Point 5 - Fit Attempt 1     ; ff    ;
; Late Wire Use - Fit Attempt 1        ; 0     ;
; Late Slack - Fit Attempt 1           ; 93870 ;
; Peak Regional Wire - Fit Attempt 1   ; 0.000 ;
; Auto Fit Point 6 - Fit Attempt 1     ; ff    ;
; Time - Fit Attempt 1                 ; 0     ;
; Time in fit_fsyn.dll - Fit Attempt 1 ; 0.157 ;
; Time in tsm_tan.dll - Fit Attempt 1  ; 0.016 ;
+--------------------------------------+-------+


+---------------------------------------------+
; Advanced Data - Routing                     ;
+-------------------------------------+-------+
; Name                                ; Value ;
+-------------------------------------+-------+
; Early Wire Use - Fit Attempt 1      ; 0     ;
; Peak Regional Wire - Fit Attempt 1  ; 0     ;
; Early Slack - Fit Attempt 1         ; 94746 ;
; Mid Slack - Fit Attempt 1           ; 94356 ;
; Late Slack - Fit Attempt 1          ; 94356 ;
; Late Wire Use - Fit Attempt 1       ; 0     ;
; Time - Fit Attempt 1                ; 0     ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.016 ;
+-------------------------------------+-------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Sat Nov 17 21:16:16 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off clkgen -c clkgen
Info: Selected device EPM1270T144C3 for design "clkgen"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM570T144C3 is compatible
Warning: No exact pin location assignment(s) for 2 pins of 2 total pins
    Info: Pin CLKout not assigned to an exact location on the device
    Info: Pin CLKin not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "CLKin" to use Global clock in PIN 18
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 1 (unused VREF, 3.30 VCCIO, 0 input, 1 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  25 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  30 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  30 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  30 pins available
Info: Starting physical synthesis optimizations for speed
Info: Physical synthesis optimizations for speed complete: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Starting physical synthesis optimizations for speed
Info: Starting physical synthesis algorithm local logic rewiring
Info: Physical synthesis algorithm local logic rewiring complete: estimated slack improvement of 0 ps
Info: Starting physical synthesis algorithm logic replication
Info: Physical synthesis algorithm logic replication complete: estimated slack improvement of 0 ps
Info: Starting physical synthesis algorithm combinational resynthesis type b
Info: Physical synthesis algorithm combinational resynthesis type b complete: estimated slack improvement of 0 ps
Info: Starting physical synthesis algorithm local logic rewiring
Info: Physical synthesis algorithm local logic rewiring complete: estimated slack improvement of 0 ps
Info: Starting physical synthesis algorithm fanout splitting
Info: Physical synthesis algorithm fanout splitting complete: estimated slack improvement of 0 ps
Info: Physical synthesis optimizations for speed complete: elapsed time is 00:00:00
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 1.094 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X13_Y8; Fanout = 3; REG Node = 'i[2]'
    Info: 2: + IC(0.725 ns) + CELL(0.369 ns) = 1.094 ns; Loc. = LAB_X13_Y8; Fanout = 2; REG Node = 'CLKref'
    Info: Total cell delay = 0.369 ns ( 33.73 % )
    Info: Total interconnect delay = 0.725 ns ( 66.27 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
    Info: The peak interconnect region extends from location X0_Y0 to location X8_Y11
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Generated suppressed messages file F:/clkgen/clkgen.fit.smsg
Info: Quartus II Fitter was successful. 0 errors, 1 warning
    Info: Allocated 170 megabytes of memory during processing
    Info: Processing ended: Sat Nov 17 21:16:18 2007
    Info: Elapsed time: 00:00:02


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in F:/clkgen/clkgen.fit.smsg.