clkgen.fit.summary

用最少的CPLD资源,用Verilog在QuartusII7.1上实现的1280分频.

Fitter Status : Successful - Sat Nov 17 21:16:18 2007
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version
Revision Name : clkgen
Top-level Entity Name : clkgen
Family : MAX II
Device : EPM1270T144C3
Timing Models : Final
Total logic elements : 11 / 1,270 ( < 1 % )
Total pins : 2 / 116 ( 2 % )
Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % )