clkgen.tan.rpt

用最少的CPLD资源,用Verilog在QuartusII7.1上实现的1280分频.

+---------------+------------+------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Minimum Slack ; From       ; To         ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+---------------+------------+------------+------------+----------+----------------------------+----------------------------+--------------------------+
; 1.024 ns      ; clk_div8   ; clk_div8   ; CLKin      ; CLKin    ; 0.000 ns                   ; -0.097 ns                  ; 0.927 ns                 ;
; 1.024 ns      ; clk_div32  ; clk_div32  ; CLKin      ; CLKin    ; 0.000 ns                   ; -0.097 ns                  ; 0.927 ns                 ;
; 1.024 ns      ; clk_div128 ; clk_div128 ; CLKin      ; CLKin    ; 0.000 ns                   ; -0.097 ns                  ; 0.927 ns                 ;
; 1.035 ns      ; clk_div4   ; clk_div4   ; CLKin      ; CLKin    ; 0.000 ns                   ; -0.097 ns                  ; 0.938 ns                 ;
; 1.035 ns      ; clk_div16  ; clk_div16  ; CLKin      ; CLKin    ; 0.000 ns                   ; -0.097 ns                  ; 0.938 ns                 ;
; 1.035 ns      ; clk_div64  ; clk_div64  ; CLKin      ; CLKin    ; 0.000 ns                   ; -0.097 ns                  ; 0.938 ns                 ;
; 1.057 ns      ; clk_div2   ; clk_div2   ; CLKin      ; CLKin    ; 0.000 ns                   ; -0.097 ns                  ; 0.960 ns                 ;
; 1.061 ns      ; i[2]       ; i[2]       ; CLKin      ; CLKin    ; 0.000 ns                   ; -0.097 ns                  ; 0.964 ns                 ;
; 1.066 ns      ; i[1]       ; i[0]       ; CLKin      ; CLKin    ; 0.000 ns                   ; -0.097 ns                  ; 0.969 ns                 ;
; 1.070 ns      ; i[2]       ; CLKref     ; CLKin      ; CLKin    ; 0.000 ns                   ; -0.097 ns                  ; 0.973 ns                 ;
; 1.080 ns      ; i[0]       ; i[1]       ; CLKin      ; CLKin    ; 0.000 ns                   ; -0.097 ns                  ; 0.983 ns                 ;
; 1.197 ns      ; CLKref     ; CLKref     ; CLKin      ; CLKin    ; 0.000 ns                   ; -0.097 ns                  ; 1.100 ns                 ;
; 1.365 ns      ; i[0]       ; i[0]       ; CLKin      ; CLKin    ; 0.000 ns                   ; -0.097 ns                  ; 1.268 ns                 ;
; 1.366 ns      ; i[0]       ; i[2]       ; CLKin      ; CLKin    ; 0.000 ns                   ; -0.097 ns                  ; 1.269 ns                 ;
; 1.373 ns      ; i[0]       ; CLKref     ; CLKin      ; CLKin    ; 0.000 ns                   ; -0.097 ns                  ; 1.276 ns                 ;
; 1.422 ns      ; i[1]       ; i[1]       ; CLKin      ; CLKin    ; 0.000 ns                   ; -0.097 ns                  ; 1.325 ns                 ;
; 1.423 ns      ; i[1]       ; CLKref     ; CLKin      ; CLKin    ; 0.000 ns                   ; -0.097 ns                  ; 1.326 ns                 ;
; 1.427 ns      ; i[1]       ; i[2]       ; CLKin      ; CLKin    ; 0.000 ns                   ; -0.097 ns                  ; 1.330 ns                 ;
; 1.433 ns      ; i[2]       ; i[0]       ; CLKin      ; CLKin    ; 0.000 ns                   ; -0.097 ns                  ; 1.336 ns                 ;
+---------------+------------+------------+------------+----------+----------------------------+----------------------------+--------------------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Sat Nov 17 21:16:24 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off clkgen -c clkgen
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found 7 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "CLKref" as buffer
    Info: Detected ripple clock "clk_div2" as buffer
    Info: Detected ripple clock "clk_div4" as buffer
    Info: Detected ripple clock "clk_div8" as buffer
    Info: Detected ripple clock "clk_div16" as buffer
    Info: Detected ripple clock "clk_div32" as buffer
    Info: Detected ripple clock "clk_div64" as buffer
Info: Found timing assignments -- calculating delays
Info: Slack time is 95.877 ns for clock "CLKin" between source register "i[2]" and destination register "i[0]"
    Info: Fmax is restricted to 304.04 MHz due to tcl and tch limits
    Info: + Largest register to register requirement is 97.213 ns
        Info: + Setup relationship between source and destination is 97.656 ns
            Info: + Latch edge is 97.656 ns
                Info: Clock period of Destination clock "CLKin" is 97.656 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
            Info: - Launch edge is 0.000 ns
                Info: Clock period of Source clock "CLKin" is 97.656 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
        Info: + Largest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLKin" to destination register is 2.388 ns
                Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_18; Fanout = 4; CLK Node = 'CLKin'
                Info: 2: + IC(1.087 ns) + CELL(0.574 ns) = 2.388 ns; Loc. = LC_X13_Y8_N2; Fanout = 4; REG Node = 'i[0]'
                Info: Total cell delay = 1.301 ns ( 54.48 % )
                Info: Total interconnect delay = 1.087 ns ( 45.52 % )
            Info: - Longest clock path from clock "CLKin" to source register is 2.388 ns
                Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_18; Fanout = 4; CLK Node = 'CLKin'
                Info: 2: + IC(1.087 ns) + CELL(0.574 ns) = 2.388 ns; Loc. = LC_X13_Y8_N1; Fanout = 3; REG Node = 'i[2]'
                Info: Total cell delay = 1.301 ns ( 54.48 % )
                Info: Total interconnect delay = 1.087 ns ( 45.52 % )
        Info: - Micro clock to output delay of source is 0.235 ns
        Info: - Micro setup delay of destination is 0.208 ns
    Info: - Longest register to register delay is 1.336 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y8_N1; Fanout = 3; REG Node = 'i[2]'
        Info: 2: + IC(0.834 ns) + CELL(0.502 ns) = 1.336 ns; Loc. = LC_X13_Y8_N2; Fanout = 4; REG Node = 'i[0]'
        Info: Total cell delay = 0.502 ns ( 37.57 % )
        Info: Total interconnect delay = 0.834 ns ( 62.43 % )
Info: No valid register-to-register data paths exist for clock "CLKout"
Info: Minimum slack time is 1.024 ns for clock "CLKin" between source register "clk_div8" and destination register "clk_div8"
    Info: + Shortest register to register delay is 0.927 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y8_N3; Fanout = 2; REG Node = 'clk_div8'
        Info: 2: + IC(0.558 ns) + CELL(0.369 ns) = 0.927 ns; Loc. = LC_X12_Y8_N3; Fanout = 2; REG Node = 'clk_div8'
        Info: Total cell delay = 0.369 ns ( 39.81 % )
        Info: Total interconnect delay = 0.558 ns ( 60.19 % )
    Info: - Smallest register to register requirement is -0.097 ns
        Info: + Hold relationship between source and destination is 0.000 ns
            Info: + Latch edge is 0.000 ns
                Info: Clock period of Destination clock "CLKin" is 97.656 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
                Info: Multicycle Hold factor for Destination register is 1
            Info: - Launch edge is 0.000 ns
                Info: Clock period of Source clock "CLKin" is 97.656 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
                Info: Multicycle Hold factor for Source register is 1
        Info: + Smallest clock skew is 0.000 ns
            Info: + Longest clock path from clock "CLKin" to destination register is 6.673 ns
                Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_18; Fanout = 4; CLK Node = 'CLKin'
                Info: 2: + IC(1.087 ns) + CELL(0.809 ns) = 2.623 ns; Loc. = LC_X13_Y8_N6; Fanout = 2; REG Node = 'CLKref'
                Info: 3: + IC(0.542 ns) + CELL(0.809 ns) = 3.974 ns; Loc. = LC_X13_Y8_N9; Fanout = 2; REG Node = 'clk_div2'
                Info: 4: + IC(0.774 ns) + CELL(0.809 ns) = 5.557 ns; Loc. = LC_X12_Y8_N2; Fanout = 2; REG Node = 'clk_div4'
                Info: 5: + IC(0.542 ns) + CELL(0.574 ns) = 6.673 ns; Loc. = LC_X12_Y8_N3; Fanout = 2; REG Node = 'clk_div8'
                Info: Total cell delay = 3.728 ns ( 55.87 % )
                Info: Total interconnect delay = 2.945 ns ( 44.13 % )
            Info: - Shortest clock path from clock "CLKin" to source register is 6.673 ns
                Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_18; Fanout = 4; CLK Node = 'CLKin'
                Info: 2: + IC(1.087 ns) + CELL(0.809 ns) = 2.623 ns; Loc. = LC_X13_Y8_N6; Fanout = 2; REG Node = 'CLKref'
                Info: 3: + IC(0.542 ns) + CELL(0.809 ns) = 3.974 ns; Loc. = LC_X13_Y8_N9; Fanout = 2; REG Node = 'clk_div2'
                Info: 4: + IC(0.774 ns) + CELL(0.809 ns) = 5.557 ns; Loc. = LC_X12_Y8_N2; Fanout = 2; REG Node = 'clk_div4'
                Info: 5: + IC(0.542 ns) + CELL(0.574 ns) = 6.673 ns; Loc. = LC_X12_Y8_N3; Fanout = 2; REG Node = 'clk_div8'
                Info: Total cell delay = 3.728 ns ( 55.87 % )
                Info: Total interconnect delay = 2.945 ns ( 44.13 % )
        Info: - Micro clock to output delay of source is 0.235 ns
        Info: + Micro hold delay of destination is 0.138 ns
Info: All timing requirements were met for slow timing model timing analysis. See Report window for more details.
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 108 megabytes of memory during processing
    Info: Processing ended: Sat Nov 17 21:16:25 2007
    Info: Elapsed time: 00:00:01