📄 clkgen.tan.rpt
字号:
Classic Timing Analyzer report for clkgen
Sat Nov 17 21:16:25 2007
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
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; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'CLKin'
6. Clock Hold: 'CLKin'
7. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-----------+----------------------------------+------------------------------------------------+----------+----------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-----------+----------------------------------+------------------------------------------------+----------+----------+------------+----------+--------------+
; Clock Setup: 'CLKin' ; 95.877 ns ; 10.24 MHz ( period = 97.656 ns ) ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; i[2] ; i[0] ; CLKin ; CLKin ; 0 ;
; Clock Hold: 'CLKin' ; 1.024 ns ; 10.24 MHz ( period = 97.656 ns ) ; N/A ; clk_div8 ; clk_div8 ; CLKin ; CLKin ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-----------+----------------------------------+------------------------------------------------+----------+----------+------------+----------+--------------+
+----------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+--------+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+--------+-------------+
; Device Name ; EPM1270T144C3 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; fmax Requirement ; 300 MHz ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; tsu Requirement ; 6 ns ; * ; * ; ;
; Clock Settings ; CLKin ; ; CLKin ; ;
; Clock Settings ; CLKout ; ; CLKout ; ;
+-------------------------------------------------------+--------------------+------+--------+-------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+---------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+---------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; CLKin ; CLKin ; User Pin ; 10.24 MHz ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; CLKout ; CLKout ; Internal Node ; 0.01 MHz ; 0.000 ns ; 0.000 ns ; CLKin ; 1 ; 1280 ; 10.000 ns ; ;
+-----------------+--------------------+---------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLKin' ;
+-----------+-----------------------------------------------+------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------+-----------------------------------------------+------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; 95.877 ns ; Restricted to 304.04 MHz ( period = 3.29 ns ) ; i[2] ; i[0] ; CLKin ; CLKin ; 97.656 ns ; 97.213 ns ; 1.336 ns ;
; 95.883 ns ; Restricted to 304.04 MHz ( period = 3.29 ns ) ; i[1] ; i[2] ; CLKin ; CLKin ; 97.656 ns ; 97.213 ns ; 1.330 ns ;
; 95.887 ns ; Restricted to 304.04 MHz ( period = 3.29 ns ) ; i[1] ; CLKref ; CLKin ; CLKin ; 97.656 ns ; 97.213 ns ; 1.326 ns ;
; 95.888 ns ; Restricted to 304.04 MHz ( period = 3.29 ns ) ; i[1] ; i[1] ; CLKin ; CLKin ; 97.656 ns ; 97.213 ns ; 1.325 ns ;
; 95.937 ns ; Restricted to 304.04 MHz ( period = 3.29 ns ) ; i[0] ; CLKref ; CLKin ; CLKin ; 97.656 ns ; 97.213 ns ; 1.276 ns ;
; 95.944 ns ; Restricted to 304.04 MHz ( period = 3.29 ns ) ; i[0] ; i[2] ; CLKin ; CLKin ; 97.656 ns ; 97.213 ns ; 1.269 ns ;
; 95.945 ns ; Restricted to 304.04 MHz ( period = 3.29 ns ) ; i[0] ; i[0] ; CLKin ; CLKin ; 97.656 ns ; 97.213 ns ; 1.268 ns ;
; 96.113 ns ; Restricted to 304.04 MHz ( period = 3.29 ns ) ; CLKref ; CLKref ; CLKin ; CLKin ; 97.656 ns ; 97.213 ns ; 1.100 ns ;
; 96.230 ns ; Restricted to 304.04 MHz ( period = 3.29 ns ) ; i[0] ; i[1] ; CLKin ; CLKin ; 97.656 ns ; 97.213 ns ; 0.983 ns ;
; 96.240 ns ; Restricted to 304.04 MHz ( period = 3.29 ns ) ; i[2] ; CLKref ; CLKin ; CLKin ; 97.656 ns ; 97.213 ns ; 0.973 ns ;
; 96.244 ns ; Restricted to 304.04 MHz ( period = 3.29 ns ) ; i[1] ; i[0] ; CLKin ; CLKin ; 97.656 ns ; 97.213 ns ; 0.969 ns ;
; 96.249 ns ; Restricted to 304.04 MHz ( period = 3.29 ns ) ; i[2] ; i[2] ; CLKin ; CLKin ; 97.656 ns ; 97.213 ns ; 0.964 ns ;
; 96.253 ns ; Restricted to 304.04 MHz ( period = 3.29 ns ) ; clk_div2 ; clk_div2 ; CLKin ; CLKin ; 97.656 ns ; 97.213 ns ; 0.960 ns ;
; 96.275 ns ; Restricted to 304.04 MHz ( period = 3.29 ns ) ; clk_div4 ; clk_div4 ; CLKin ; CLKin ; 97.656 ns ; 97.213 ns ; 0.938 ns ;
; 96.275 ns ; Restricted to 304.04 MHz ( period = 3.29 ns ) ; clk_div16 ; clk_div16 ; CLKin ; CLKin ; 97.656 ns ; 97.213 ns ; 0.938 ns ;
; 96.275 ns ; Restricted to 304.04 MHz ( period = 3.29 ns ) ; clk_div64 ; clk_div64 ; CLKin ; CLKin ; 97.656 ns ; 97.213 ns ; 0.938 ns ;
; 96.286 ns ; Restricted to 304.04 MHz ( period = 3.29 ns ) ; clk_div8 ; clk_div8 ; CLKin ; CLKin ; 97.656 ns ; 97.213 ns ; 0.927 ns ;
; 96.286 ns ; Restricted to 304.04 MHz ( period = 3.29 ns ) ; clk_div32 ; clk_div32 ; CLKin ; CLKin ; 97.656 ns ; 97.213 ns ; 0.927 ns ;
; 96.286 ns ; Restricted to 304.04 MHz ( period = 3.29 ns ) ; clk_div128 ; clk_div128 ; CLKin ; CLKin ; 97.656 ns ; 97.213 ns ; 0.927 ns ;
+-----------+-----------------------------------------------+------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'CLKin' ;
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