📄 prev_cmp_clkgen.qmsg
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off clkgen -c clkgen " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off clkgen -c clkgen" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "120 " "Info: Allocated 120 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Nov 17 21:16:23 2007 " "Info: Processing ended: Sat Nov 17 21:16:23 2007" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Nov 17 21:16:24 2007 " "Info: Processing started: Sat Nov 17 21:16:24 2007" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off clkgen -c clkgen " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off clkgen -c clkgen" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "7 " "Warning: Found 7 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "CLKref " "Info: Detected ripple clock \"CLKref\" as buffer" { } { { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 19 -1 0 } } { "d:/altera71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera71/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLKref" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clk_div2 " "Info: Detected ripple clock \"clk_div2\" as buffer" { } { { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 35 0 0 } } { "d:/altera71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera71/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_div2" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clk_div4 " "Info: Detected ripple clock \"clk_div4\" as buffer" { } { { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 36 0 0 } } { "d:/altera71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera71/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_div4" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clk_div8 " "Info: Detected ripple clock \"clk_div8\" as buffer" { } { { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 37 0 0 } } { "d:/altera71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera71/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_div8" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clk_div16 " "Info: Detected ripple clock \"clk_div16\" as buffer" { } { { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 38 0 0 } } { "d:/altera71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera71/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_div16" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clk_div32 " "Info: Detected ripple clock \"clk_div32\" as buffer" { } { { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 39 0 0 } } { "d:/altera71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera71/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_div32" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clk_div64 " "Info: Detected ripple clock \"clk_div64\" as buffer" { } { { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 40 0 0 } } { "d:/altera71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera71/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_div64" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" { } { } 0 0 "Found timing assignments -- calculating delays" 0 0 "" 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "CLKin register i\[2\] register i\[0\] 95.877 ns " "Info: Slack time is 95.877 ns for clock \"CLKin\" between source register \"i\[2\]\" and destination register \"i\[0\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT_RESTRICTED" "304.04 MHz " "Info: Fmax is restricted to 304.04 MHz due to tcl and tch limits" { } { } 0 0 "Fmax is restricted to %1!s! due to tcl and tch limits" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "97.213 ns + Largest register register " "Info: + Largest register to register requirement is 97.213 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "97.656 ns + " "Info: + Setup relationship between source and destination is 97.656 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 97.656 ns " "Info: + Latch edge is 97.656 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLKin 97.656 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"CLKin\" is 97.656 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLKin 97.656 ns 0.000 ns 50 " "Info: Clock period of Source clock \"CLKin\" is 97.656 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLKin destination 2.388 ns + Shortest register " "Info: + Shortest clock path from clock \"CLKin\" to destination register is 2.388 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns CLKin 1 CLK PIN_18 4 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_18; Fanout = 4; CLK Node = 'CLKin'" { } { { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLKin } "NODE_NAME" } } { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.087 ns) + CELL(0.574 ns) 2.388 ns i\[0\] 2 REG LC_X13_Y8_N2 4 " "Info: 2: + IC(1.087 ns) + CELL(0.574 ns) = 2.388 ns; Loc. = LC_X13_Y8_N2; Fanout = 4; REG Node = 'i\[0\]'" { } { { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "1.661 ns" { CLKin i[0] } "NODE_NAME" } } { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.301 ns ( 54.48 % ) " "Info: Total cell delay = 1.301 ns ( 54.48 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.087 ns ( 45.52 % ) " "Info: Total interconnect delay = 1.087 ns ( 45.52 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "2.388 ns" { CLKin i[0] } "NODE_NAME" } } { "d:/altera71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera71/quartus/bin/Technology_Viewer.qrui" "2.388 ns" { CLKin CLKin~combout i[0] } { 0.000ns 0.000ns 1.087ns } { 0.000ns 0.727ns 0.574ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLKin source 2.388 ns - Longest register " "Info: - Longest clock path from clock \"CLKin\" to source register is 2.388 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns CLKin 1 CLK PIN_18 4 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_18; Fanout = 4; CLK Node = 'CLKin'" { } { { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLKin } "NODE_NAME" } } { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.087 ns) + CELL(0.574 ns) 2.388 ns i\[2\] 2 REG LC_X13_Y8_N1 3 " "Info: 2: + IC(1.087 ns) + CELL(0.574 ns) = 2.388 ns; Loc. = LC_X13_Y8_N1; Fanout = 3; REG Node = 'i\[2\]'" { } { { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "1.661 ns" { CLKin i[2] } "NODE_NAME" } } { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.301 ns ( 54.48 % ) " "Info: Total cell delay = 1.301 ns ( 54.48 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.087 ns ( 45.52 % ) " "Info: Total interconnect delay = 1.087 ns ( 45.52 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "2.388 ns" { CLKin i[2] } "NODE_NAME" } } { "d:/altera71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera71/quartus/bin/Technology_Viewer.qrui" "2.388 ns" { CLKin CLKin~combout i[2] } { 0.000ns 0.000ns 1.087ns } { 0.000ns 0.727ns 0.574ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "2.388 ns" { CLKin i[0] } "NODE_NAME" } } { "d:/altera71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera71/quartus/bin/Technology_Viewer.qrui" "2.388 ns" { CLKin CLKin~combout i[0] } { 0.000ns 0.000ns 1.087ns } { 0.000ns 0.727ns 0.574ns } "" } } { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "2.388 ns" { CLKin i[2] } "NODE_NAME" } } { "d:/altera71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera71/quartus/bin/Technology_Viewer.qrui" "2.388 ns" { CLKin CLKin~combout i[2] } { 0.000ns 0.000ns 1.087ns } { 0.000ns 0.727ns 0.574ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.235 ns - " "Info: - Micro clock to output delay of source is 0.235 ns" { } { { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 23 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.208 ns - " "Info: - Micro setup delay of destination is 0.208 ns" { } { { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 23 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "2.388 ns" { CLKin i[0] } "NODE_NAME" } } { "d:/altera71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera71/quartus/bin/Technology_Viewer.qrui" "2.388 ns" { CLKin CLKin~combout i[0] } { 0.000ns 0.000ns 1.087ns } { 0.000ns 0.727ns 0.574ns } "" } } { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "2.388 ns" { CLKin i[2] } "NODE_NAME" } } { "d:/altera71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera71/quartus/bin/Technology_Viewer.qrui" "2.388 ns" { CLKin CLKin~combout i[2] } { 0.000ns 0.000ns 1.087ns } { 0.000ns 0.727ns 0.574ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.336 ns - Longest register register " "Info: - Longest register to register delay is 1.336 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns i\[2\] 1 REG LC_X13_Y8_N1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y8_N1; Fanout = 3; REG Node = 'i\[2\]'" { } { { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i[2] } "NODE_NAME" } } { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.834 ns) + CELL(0.502 ns) 1.336 ns i\[0\] 2 REG LC_X13_Y8_N2 4 " "Info: 2: + IC(0.834 ns) + CELL(0.502 ns) = 1.336 ns; Loc. = LC_X13_Y8_N2; Fanout = 4; REG Node = 'i\[0\]'" { } { { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "1.336 ns" { i[2] i[0] } "NODE_NAME" } } { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.502 ns ( 37.57 % ) " "Info: Total cell delay = 0.502 ns ( 37.57 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.834 ns ( 62.43 % ) " "Info: Total interconnect delay = 0.834 ns ( 62.43 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "1.336 ns" { i[2] i[0] } "NODE_NAME" } } { "d:/altera71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera71/quartus/bin/Technology_Viewer.qrui" "1.336 ns" { i[2] i[0] } { 0.000ns 0.834ns } { 0.000ns 0.502ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "2.388 ns" { CLKin i[0] } "NODE_NAME" } } { "d:/altera71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera71/quartus/bin/Technology_Viewer.qrui" "2.388 ns" { CLKin CLKin~combout i[0] } { 0.000ns 0.000ns 1.087ns } { 0.000ns 0.727ns 0.574ns } "" } } { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "2.388 ns" { CLKin i[2] } "NODE_NAME" } } { "d:/altera71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera71/quartus/bin/Technology_Viewer.qrui" "2.388 ns" { CLKin CLKin~combout i[2] } { 0.000ns 0.000ns 1.087ns } { 0.000ns 0.727ns 0.574ns } "" } } { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "1.336 ns" { i[2] i[0] } "NODE_NAME" } } { "d:/altera71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera71/quartus/bin/Technology_Viewer.qrui" "1.336 ns" { i[2] i[0] } { 0.000ns 0.834ns } { 0.000ns 0.502ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "CLKout " "Info: No valid register-to-register data paths exist for clock \"CLKout\"" { } { } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "CLKin register clk_div8 register clk_div8 1.024 ns " "Info: Minimum slack time is 1.024 ns for clock \"CLKin\" between source register \"clk_div8\" and destination register \"clk_div8\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.927 ns + Shortest register register " "Info: + Shortest register to register delay is 0.927 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_div8 1 REG LC_X12_Y8_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y8_N3; Fanout = 2; REG Node = 'clk_div8'" { } { { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_div8 } "NODE_NAME" } } { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 37 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.558 ns) + CELL(0.369 ns) 0.927 ns clk_div8 2 REG LC_X12_Y8_N3 2 " "Info: 2: + IC(0.558 ns) + CELL(0.369 ns) = 0.927 ns; Loc. = LC_X12_Y8_N3; Fanout = 2; REG Node = 'clk_div8'" { } { { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "0.927 ns" { clk_div8 clk_div8 } "NODE_NAME" } } { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 37 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.369 ns ( 39.81 % ) " "Info: Total cell delay = 0.369 ns ( 39.81 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.558 ns ( 60.19 % ) " "Info: Total interconnect delay = 0.558 ns ( 60.19 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "0.927 ns" { clk_div8 clk_div8 } "NODE_NAME" } } { "d:/altera71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera71/quartus/bin/Technology_Viewer.qrui" "0.927 ns" { clk_div8 clk_div8 } { 0.000ns 0.558ns } { 0.000ns 0.369ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.097 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.097 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLKin 97.656 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"CLKin\" is 97.656 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLKin 97.656 ns 0.000 ns 50 " "Info: Clock period of Source clock \"CLKin\" is 97.656 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} } { } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLKin destination 6.673 ns + Longest register " "Info: + Longest clock path from clock \"CLKin\" to destination register is 6.673 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns CLKin 1 CLK PIN_18 4 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_18; Fanout = 4; CLK Node = 'CLKin'" { } { { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLKin } "NODE_NAME" } } { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.087 ns) + CELL(0.809 ns) 2.623 ns CLKref 2 REG LC_X13_Y8_N6 2 " "Info: 2: + IC(1.087 ns) + CELL(0.809 ns) = 2.623 ns; Loc. = LC_X13_Y8_N6; Fanout = 2; REG Node = 'CLKref'" { } { { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "1.896 ns" { CLKin CLKref } "NODE_NAME" } } { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.542 ns) + CELL(0.809 ns) 3.974 ns clk_div2 3 REG LC_X13_Y8_N9 2 " "Info: 3: + IC(0.542 ns) + CELL(0.809 ns) = 3.974 ns; Loc. = LC_X13_Y8_N9; Fanout = 2; REG Node = 'clk_div2'" { } { { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "1.351 ns" { CLKref clk_div2 } "NODE_NAME" } } { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 35 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.809 ns) 5.557 ns clk_div4 4 REG LC_X12_Y8_N2 2 " "Info: 4: + IC(0.774 ns) + CELL(0.809 ns) = 5.557 ns; Loc. = LC_X12_Y8_N2; Fanout = 2; REG Node = 'clk_div4'" { } { { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "1.583 ns" { clk_div2 clk_div4 } "NODE_NAME" } } { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 36 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.542 ns) + CELL(0.574 ns) 6.673 ns clk_div8 5 REG LC_X12_Y8_N3 2 " "Info: 5: + IC(0.542 ns) + CELL(0.574 ns) = 6.673 ns; Loc. = LC_X12_Y8_N3; Fanout = 2; REG Node = 'clk_div8'" { } { { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "1.116 ns" { clk_div4 clk_div8 } "NODE_NAME" } } { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 37 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.728 ns ( 55.87 % ) " "Info: Total cell delay = 3.728 ns ( 55.87 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.945 ns ( 44.13 % ) " "Info: Total interconnect delay = 2.945 ns ( 44.13 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "6.673 ns" { CLKin CLKref clk_div2 clk_div4 clk_div8 } "NODE_NAME" } } { "d:/altera71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera71/quartus/bin/Technology_Viewer.qrui" "6.673 ns" { CLKin CLKin~combout CLKref clk_div2 clk_div4 clk_div8 } { 0.000ns 0.000ns 1.087ns 0.542ns 0.774ns 0.542ns } { 0.000ns 0.727ns 0.809ns 0.809ns 0.809ns 0.574ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLKin source 6.673 ns - Shortest register " "Info: - Shortest clock path from clock \"CLKin\" to source register is 6.673 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns CLKin 1 CLK PIN_18 4 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_18; Fanout = 4; CLK Node = 'CLKin'" { } { { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLKin } "NODE_NAME" } } { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.087 ns) + CELL(0.809 ns) 2.623 ns CLKref 2 REG LC_X13_Y8_N6 2 " "Info: 2: + IC(1.087 ns) + CELL(0.809 ns) = 2.623 ns; Loc. = LC_X13_Y8_N6; Fanout = 2; REG Node = 'CLKref'" { } { { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "1.896 ns" { CLKin CLKref } "NODE_NAME" } } { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.542 ns) + CELL(0.809 ns) 3.974 ns clk_div2 3 REG LC_X13_Y8_N9 2 " "Info: 3: + IC(0.542 ns) + CELL(0.809 ns) = 3.974 ns; Loc. = LC_X13_Y8_N9; Fanout = 2; REG Node = 'clk_div2'" { } { { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "1.351 ns" { CLKref clk_div2 } "NODE_NAME" } } { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 35 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.809 ns) 5.557 ns clk_div4 4 REG LC_X12_Y8_N2 2 " "Info: 4: + IC(0.774 ns) + CELL(0.809 ns) = 5.557 ns; Loc. = LC_X12_Y8_N2; Fanout = 2; REG Node = 'clk_div4'" { } { { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "1.583 ns" { clk_div2 clk_div4 } "NODE_NAME" } } { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 36 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.542 ns) + CELL(0.574 ns) 6.673 ns clk_div8 5 REG LC_X12_Y8_N3 2 " "Info: 5: + IC(0.542 ns) + CELL(0.574 ns) = 6.673 ns; Loc. = LC_X12_Y8_N3; Fanout = 2; REG Node = 'clk_div8'" { } { { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "1.116 ns" { clk_div4 clk_div8 } "NODE_NAME" } } { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 37 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.728 ns ( 55.87 % ) " "Info: Total cell delay = 3.728 ns ( 55.87 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.945 ns ( 44.13 % ) " "Info: Total interconnect delay = 2.945 ns ( 44.13 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "6.673 ns" { CLKin CLKref clk_div2 clk_div4 clk_div8 } "NODE_NAME" } } { "d:/altera71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera71/quartus/bin/Technology_Viewer.qrui" "6.673 ns" { CLKin CLKin~combout CLKref clk_div2 clk_div4 clk_div8 } { 0.000ns 0.000ns 1.087ns 0.542ns 0.774ns 0.542ns } { 0.000ns 0.727ns 0.809ns 0.809ns 0.809ns 0.574ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "6.673 ns" { CLKin CLKref clk_div2 clk_div4 clk_div8 } "NODE_NAME" } } { "d:/altera71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera71/quartus/bin/Technology_Viewer.qrui" "6.673 ns" { CLKin CLKin~combout CLKref clk_div2 clk_div4 clk_div8 } { 0.000ns 0.000ns 1.087ns 0.542ns 0.774ns 0.542ns } { 0.000ns 0.727ns 0.809ns 0.809ns 0.809ns 0.574ns } "" } } { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "6.673 ns" { CLKin CLKref clk_div2 clk_div4 clk_div8 } "NODE_NAME" } } { "d:/altera71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera71/quartus/bin/Technology_Viewer.qrui" "6.673 ns" { CLKin CLKin~combout CLKref clk_div2 clk_div4 clk_div8 } { 0.000ns 0.000ns 1.087ns 0.542ns 0.774ns 0.542ns } { 0.000ns 0.727ns 0.809ns 0.809ns 0.809ns 0.574ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.235 ns - " "Info: - Micro clock to output delay of source is 0.235 ns" { } { { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 37 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.138 ns + " "Info: + Micro hold delay of destination is 0.138 ns" { } { { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 37 0 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "6.673 ns" { CLKin CLKref clk_div2 clk_div4 clk_div8 } "NODE_NAME" } } { "d:/altera71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera71/quartus/bin/Technology_Viewer.qrui" "6.673 ns" { CLKin CLKin~combout CLKref clk_div2 clk_div4 clk_div8 } { 0.000ns 0.000ns 1.087ns 0.542ns 0.774ns 0.542ns } { 0.000ns 0.727ns 0.809ns 0.809ns 0.809ns 0.574ns } "" } } { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "6.673 ns" { CLKin CLKref clk_div2 clk_div4 clk_div8 } "NODE_NAME" } } { "d:/altera71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera71/quartus/bin/Technology_Viewer.qrui" "6.673 ns" { CLKin CLKin~combout CLKref clk_div2 clk_div4 clk_div8 } { 0.000ns 0.000ns 1.087ns 0.542ns 0.774ns 0.542ns } { 0.000ns 0.727ns 0.809ns 0.809ns 0.809ns 0.574ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} } { { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "0.927 ns" { clk_div8 clk_div8 } "NODE_NAME" } } { "d:/altera71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera71/quartus/bin/Technology_Viewer.qrui" "0.927 ns" { clk_div8 clk_div8 } { 0.000ns 0.558ns } { 0.000ns 0.369ns } "" } } { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "6.673 ns" { CLKin CLKref clk_div2 clk_div4 clk_div8 } "NODE_NAME" } } { "d:/altera71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera71/quartus/bin/Technology_Viewer.qrui" "6.673 ns" { CLKin CLKin~combout CLKref clk_div2 clk_div4 clk_div8 } { 0.000ns 0.000ns 1.087ns 0.542ns 0.774ns 0.542ns } { 0.000ns 0.727ns 0.809ns 0.809ns 0.809ns 0.574ns } "" } } { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "6.673 ns" { CLKin CLKref clk_div2 clk_div4 clk_div8 } "NODE_NAME" } } { "d:/altera71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera71/quartus/bin/Technology_Viewer.qrui" "6.673 ns" { CLKin CLKin~combout CLKref clk_div2 clk_div4 clk_div8 } { 0.000ns 0.000ns 1.087ns 0.542ns 0.774ns 0.542ns } { 0.000ns 0.727ns 0.809ns 0.809ns 0.809ns 0.574ns } "" } } } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITAN_REQUIREMENTS_MET_SLOW" "" "Info: All timing requirements were met for slow timing model timing analysis. See Report window for more details." { } { } 0 0 "All timing requirements were met for slow timing model timing analysis. See Report window for more details." 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "108 " "Info: Allocated 108 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Nov 17 21:16:25 2007 " "Info: Processing ended: Sat Nov 17 21:16:25 2007" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 3 s " "Info: Quartus II Full Compilation was successful. 0 errors, 3 warnings" { } { } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
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