prev_cmp_clkgen.qmsg

用最少的CPLD资源,用Verilog在QuartusII7.1上实现的1280分频.

{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_START" "logic replication " "Info: Starting physical synthesis algorithm logic replication" {  } {  } 0 0 "Starting physical synthesis algorithm %1!s!" 0 0 "" 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_END_SLACK" "logic replication 0 " "Info: Physical synthesis algorithm logic replication complete: estimated slack improvement of 0 ps" {  } {  } 0 0 "Physical synthesis algorithm %1!s! complete: estimated slack improvement of %2!d! ps" 0 0 "" 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_START" "combinational resynthesis type b " "Info: Starting physical synthesis algorithm combinational resynthesis type b" {  } {  } 0 0 "Starting physical synthesis algorithm %1!s!" 0 0 "" 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_END_SLACK" "combinational resynthesis type b 0 " "Info: Physical synthesis algorithm combinational resynthesis type b complete: estimated slack improvement of 0 ps" {  } {  } 0 0 "Physical synthesis algorithm %1!s! complete: estimated slack improvement of %2!d! ps" 0 0 "" 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_START" "local logic rewiring " "Info: Starting physical synthesis algorithm local logic rewiring" {  } {  } 0 0 "Starting physical synthesis algorithm %1!s!" 0 0 "" 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_END_SLACK" "local logic rewiring 0 " "Info: Physical synthesis algorithm local logic rewiring complete: estimated slack improvement of 0 ps" {  } {  } 0 0 "Physical synthesis algorithm %1!s! complete: estimated slack improvement of %2!d! ps" 0 0 "" 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_START" "fanout splitting " "Info: Starting physical synthesis algorithm fanout splitting" {  } {  } 0 0 "Starting physical synthesis algorithm %1!s!" 0 0 "" 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_END_SLACK" "fanout splitting 0 " "Info: Physical synthesis algorithm fanout splitting complete: estimated slack improvement of 0 ps" {  } {  } 0 0 "Physical synthesis algorithm %1!s! complete: estimated slack improvement of %2!d! ps" 0 0 "" 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_END" "speed 00:00:00 " "Info: Physical synthesis optimizations for speed complete: elapsed time is 00:00:00" {  } {  } 0 0 "Physical synthesis optimizations for %1!s! complete: elapsed time is %2!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "1.094 ns register register " "Info: Estimated most critical path is register to register delay of 1.094 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns i\[2\] 1 REG LAB_X13_Y8 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X13_Y8; Fanout = 3; REG Node = 'i\[2\]'" {  } { { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "" { i[2] } "NODE_NAME" } } { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.725 ns) + CELL(0.369 ns) 1.094 ns CLKref 2 REG LAB_X13_Y8 2 " "Info: 2: + IC(0.725 ns) + CELL(0.369 ns) = 1.094 ns; Loc. = LAB_X13_Y8; Fanout = 2; REG Node = 'CLKref'" {  } { { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "1.094 ns" { i[2] CLKref } "NODE_NAME" } } { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.369 ns ( 33.73 % ) " "Info: Total cell delay = 0.369 ns ( 33.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.725 ns ( 66.27 % ) " "Info: Total interconnect delay = 0.725 ns ( 66.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "1.094 ns" { i[2] CLKref } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X0_Y0 X8_Y11 " "Info: The peak interconnect region extends from location X0_Y0 to location X8_Y11" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/clkgen/clkgen.fit.smsg " "Info: Generated suppressed messages file F:/clkgen/clkgen.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "170 " "Info: Allocated 170 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Nov 17 21:16:18 2007 " "Info: Processing ended: Sat Nov 17 21:16:18 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Nov 17 21:16:19 2007 " "Info: Processing started: Sat Nov 17 21:16:19 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}