prev_cmp_clkgen.qmsg

用最少的CPLD资源,用Verilog在QuartusII7.1上实现的1280分频.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Nov 17 21:16:14 2007 " "Info: Processing started: Sat Nov 17 21:16:14 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clkgen -c clkgen " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clkgen -c clkgen" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "clkgen.v(23) " "Warning (10268): Verilog HDL information at clkgen.v(23): Always Construct contains both blocking and non-blocking assignments" {  } { { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 23 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clkgen.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clkgen.v" { { "Info" "ISGN_ENTITY_NAME" "1 clkgen " "Info: Found entity 1: clkgen" {  } { { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 13 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "clkgen " "Info: Elaborating entity \"clkgen\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 clkgen.v(30) " "Warning (10230): Verilog HDL assignment warning at clkgen.v(30): truncated value with size 32 to match size of target (3)" {  } { { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 30 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "13 " "Info: Implemented 13 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "11 " "Info: Implemented 11 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "136 " "Info: Allocated 136 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Nov 17 21:16:15 2007 " "Info: Processing ended: Sat Nov 17 21:16:15 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Nov 17 21:16:16 2007 " "Info: Processing started: Sat Nov 17 21:16:16 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off clkgen -c clkgen " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off clkgen -c clkgen" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "clkgen EPM1270T144C3 " "Info: Selected device EPM1270T144C3 for design \"clkgen\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144C3 " "Info: Device EPM570T144C3 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0}
{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "2 2 " "Warning: No exact pin location assignment(s) for 2 pins of 2 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CLKout " "Info: Pin CLKout not assigned to an exact location on the device" {  } { { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 15 -1 0 } } { "d:/altera71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera71/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLKout" } } } } { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLKout } "NODE_NAME" } } { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLKout } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CLKin " "Info: Pin CLKin not assigned to an exact location on the device" {  } { { "clkgen.v" "" { Text "F:/clkgen/clkgen.v" 14 -1 0 } } { "d:/altera71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera71/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLKin" } } } } { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLKin } "NODE_NAME" } } { "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLKin } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0}