clkgen.v.bak

用最少的CPLD资源,用Verilog在QuartusII7.1上实现的1280分频.

//**********************************************************************************//
// This test module used to generate a clock based on a priliminary sysclk			//
// 1). Requirements:																//
//		i). Input: 10.24MHz															//
//		ii). Output: 8KHz, 50% ratio												//
// 2). Analysis and implemention:													//
//		i). 8KHz will occurs 1280 periods of 10.24MHz Clock							//
//			excute a 256-time divde, get a 5*8KHz Clock, since 256*5*8K=10.24M		//
//		ii).To get a 50% ratio clock from a 5-Cycle clock, we just need to promote	//
//			at the first posedge and invert at the 3rd negedge of the ref-clock. 	//
//**********************************************************************************//

module clkgen (CLKin, CLKout);
input		CLKin;				// 10MHz
output 		CLKout;				// 8KHz

wire		CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7;
reg	[2:0]	i = 3'd0;
reg			CLKref;

always @(posedge CLKin)									//1.024M
begin 
	if (i == 3'd4) begin
		CLKref = ~CLKref;
		i <= 0;
	end
	else
		i <= i + 1;
end

// Frequency divide
dff clk_div2	(.d(~CLK1), .clk(CLKref), .q(CLK1)),	//512K
	clk_div4	(.d(~CLK2), .clk(CLK1), .q(CLK2)),		//256K
	clk_div8	(.d(~CLK3), .clk(CLK2), .q(CLK3)),		//128K
	clk_div16	(.d(~CLK4), .clk(CLK3), .q(CLK4)),		//64K
	clk_div32	(.d(~CLK5), .clk(CLK4), .q(CLK5)),		//32K
	clk_div64	(.d(~CLK6), .clk(CLK5), .q(CLK6)),		//16K
	clk_div128	(.d(~CLK7), .clk(CLK6), .q(CLK7));		//8K

assign CLKout = CLK7;

endmodule


/*******************************************************************************
//input		nRST;
//reg [4:0]	state;
//reg		CLKout = 1'b0;

// Declare states
parameter	S0 = 5'b00001,
			S1 = 5'b00010,
			S2 = 5'b00100,
			S3 = 5'b01000,
			S4 = 5'b10000;

// Output depends only on the state
always @ (state) begin
	case (state)
		S0: 
			CLKout <= 1'b1;
		S1:
			CLKout <= 1'b1;
		S2:
			CLKout <= CLK8;
		S3:
			CLKout <= 1'b0;
		S4:
			CLKout <= 1'b0;
		default:
			CLKout <= 1'b0;
	endcase
end

// Determine the next state
always @ (posedge CLK8 or negedge nRST) begin
	if (~nRST)
		state = S0;
	else
		case (state)
			S0:
				state = S1;
			S1:
				state = S2;
			S2:
				state = S3;
			S3:
				state = S4;
			S4:
				state = S0;				
		endcase
end
endmodule
*/