wb_sdram.v

sdram controller.verilog

// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "sdram_defines.v"
	
module wb_sdram (
	wb_clk_i, 
    wb_rst_i,

	wb_dat_i, 
	wb_dat_o, 
	wb_adr_i, 
	wb_sel_i, 
	wb_we_i, 
	wb_cyc_i,
	wb_stb_i, 
	wb_ack_o, 
	wb_err_o,
	
	mem_clk_pad_o,
	mem_dat_pad_i,
	mem_dat_pad_o,
	mem_doe_pad_o,
	mem_adr_pad_o ,
	mem_wen_pad_o ,
	mem_csn_pad_o ,
	mem_dqmn_pad_o,
	mem_ras_pad_o,
	mem_cas_pad_o,
	mem_cke_pad_o,
	
	sd_pwrup,
	sd_go,
	sd_busy,
	sd_do_refresh
	);
	
//}} End of automatically maintained section

// --------------------------------------
// WISHBONE MEMORY INTERFACE
input			wb_clk_i;
input			wb_rst_i;
input	[31:0]	wb_dat_i;
output	[31:0]	wb_dat_o;
input	[31:0]	wb_adr_i;
input	[3:0]	wb_sel_i;
input			wb_we_i;
input			wb_cyc_i;
input			wb_stb_i;
output			wb_ack_o;
output			wb_err_o;
 
// --------------------------------------
// Memory Bus Signals
output			mem_clk_pad_o;
input	[31:0]	mem_dat_pad_i;
output	[31:0]	mem_dat_pad_o;
output			mem_doe_pad_o;
output	[14:0]	mem_adr_pad_o;
output			mem_wen_pad_o;
output			mem_csn_pad_o;
output	[3:0]	mem_dqmn_pad_o;
output			mem_ras_pad_o;
output			mem_cas_pad_o;
output			mem_cke_pad_o;

output			sd_pwrup;
input			sd_go;
output			sd_busy;
output			sd_do_refresh;

assign wb_err_o = 1'b0;
assign mem_clk_pad_o = wb_clk_i;

wire	[31:0]	sdwb_adr_i;
assign sdwb_adr_i = {6'b000000,wb_adr_i[25:0]};

reg				mem_wen_pad_o;
reg		[14:0]	mem_adr_pad_o;
reg		[31:0]	mem_dat_pad_o;
reg				mem_doe_pad_o;
reg		[3:0]	mem_dqmn_pad_o;

wire	[12:0]	sd_adr_o;
wire	[1:0]	sd_ba_o ;
wire	[31:0]	sd_dat_o;
wire			sd_dat_oe_o;
wire	[3:0]	sd_dqm_o;
wire			assert_we;

sdram_top i_sdram_top
(
	.wb_clk_i		(wb_clk_i),
	.wb_rst_i		(wb_rst_i),
	.wb_dat_i		(wb_dat_i),
	.wb_dat_o		(wb_dat_o),
	.wb_ack_o		(wb_ack_o),
	.wb_sel_i		(wb_sel_i),
	.wb_adr_i		(sdwb_adr_i),
	.wb_we_i		(wb_we_i),
	.wb_cyc_i		(wb_cyc_i),
	.wb_stb_i		(wb_stb_i),

	.mem_clk_i		(wb_clk_i),
	.sd_adr_o		(sd_adr_o),
	.sd_ba_o		(sd_ba_o),
	.sd_dat_o		(sd_dat_o),
	.sd_dat_i		(mem_dat_pad_i),
	.sd_dat_oe_o	(sd_dat_oe_o),
	.sd_cs_o		(mem_csn_pad_o),
	.sd_ras_o		(mem_ras_pad_o),
	.sd_cas_o		(mem_cas_pad_o),
	.sd_cke_o		(mem_cke_pad_o),
	.sd_dqm_o		(sd_dqm_o),
	
	.pwrup			(sd_pwrup),
	.go				(sd_go),
	.busy			(sd_busy),

	.refresh_timer_val                  (`MEM_IF_REFRESH_TIMER_RST_VAL),
	.ras2cas_delay_val                  (`MEM_IF_RAS2CAS_DELAY_RST_VAL),
	.refresh2anything_delay_val         (`MEM_IF_REFRESH2ANYTHING_DELAY_RST_VAL),
	.row_active_time_val                (`MEM_IF_ROW_ACTIVE_TIME_RST_VAL),
	.last_data_in_to_row_precharge_val  (`MEM_IF_LAST_DATA_IN_TO_ROW_PRECHARGE_RST_VAL),
	.precharge_to_ras_val               (`MEM_IF_PRECHARGE_TO_RAS_RST_VAL),
	
	.do_refresh		(sd_do_refresh),
	.load_address	(),
	.load_data		(),
	.load_dqm		(),
	.assert_we		(assert_we)
);

// we
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if (wb_rst_i)
        mem_wen_pad_o <=  1'b1 ;
    else
        mem_wen_pad_o <=  !assert_we ;
end

// adr
wire   [14:0] mem_adr_o = {sd_ba_o, sd_adr_o};
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if (wb_rst_i)
        mem_adr_pad_o <= #1 0 ;
    else
        mem_adr_pad_o <= #1 mem_adr_o ;
end

// dat
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if (wb_rst_i)
        mem_dat_pad_o <= #1 32'hFFFF_FFFF ;
    else
        mem_dat_pad_o <= #1 sd_dat_o ;
end


// doe
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if (wb_rst_i)
        mem_doe_pad_o <= #1 1'b0 ;
    else
        mem_doe_pad_o <= #1 sd_dat_oe_o ;
end

// dqm
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if (wb_rst_i)
        mem_dqmn_pad_o <= #1 4'hF ;
    else
        mem_dqmn_pad_o <= #1 sd_dqm_o ;
end

// -- Enter your statements here -- //

endmodule