sdram_top.v

sdram controller.verilog

// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
module sdram_top
(
    wb_clk_i,
    wb_rst_i,

    wb_dat_i,
    wb_dat_o,
    wb_ack_o,
    wb_sel_i,
    wb_adr_i,
    wb_we_i,
    wb_cyc_i,
    wb_stb_i,

    mem_clk_i,

    sd_adr_o,
    sd_ba_o,
    sd_dat_o,
    sd_dat_i,
    sd_dat_oe_o,
    sd_cs_o,
    sd_ras_o,
    sd_cas_o,
    sd_cke_o,
    sd_dqm_o,
    pwrup,
    go,
    busy,
    refresh_timer_val,
    ras2cas_delay_val,
    refresh2anything_delay_val,
    row_active_time_val,
    last_data_in_to_row_precharge_val,
    precharge_to_ras_val,
    do_refresh,
    load_address,
    load_data,
    load_dqm,
    assert_we
);

input           wb_clk_i ;
input           wb_rst_i ;

input   [31:0]  wb_dat_i ;
output  [31:0]  wb_dat_o ;
output          wb_ack_o ;
input   [3:0]   wb_sel_i ;
input   [31:0]  wb_adr_i ;
input           wb_we_i  ;
input           wb_cyc_i ;
input           wb_stb_i ;

input           mem_clk_i ;

output  [12:0]  sd_adr_o ;
output  [1:0]   sd_ba_o  ;
output  [31:0]  sd_dat_o ;
input   [31:0]  sd_dat_i ;
output          sd_dat_oe_o ;
output          sd_cs_o ;
output          sd_ras_o ;
output          sd_cas_o ;
output          sd_cke_o ;
assign          sd_cke_o = 1'b1 ;
output  [3:0]   sd_dqm_o ;
output          pwrup    ;
input           go       ;
output          busy     ;
input   [15:0]  refresh_timer_val ;
input   [1:0]   ras2cas_delay_val ;
input   [3:0]   refresh2anything_delay_val ;
input   [3:0]   row_active_time_val ;
input   [1:0]   last_data_in_to_row_precharge_val ;
input   [1:0]   precharge_to_ras_val ;
output          do_refresh ;

output load_address;
output load_data;
output load_dqm;
output assert_we;

wire do_mode_set ;
wire do_read ;
wire do_write ;
wire doing_refresh ;
wire [1:0] sd_addx_mux ;
wire [1:0] sd_addx10_mux ;
wire sd_rd_ena ;
wire [2:0] modereg_cas_latency ;
wire [2:0] modereg_burst_length ;
wire [3:0] decoded_dqm ;
wire do_write_ack ;
wire do_read_ack ;

sdram_cnt i_sdram_cnt
(
    // system level stuff
	.sys_rst_l(!wb_rst_i),
	.sys_clk(mem_clk_i),

    // SDRAM connections
    .sd_cs_l(sd_cs_o),
	.sd_ras_l(sd_ras_o),
	.sd_cas_l(sd_cas_o),
	.sd_dqm(sd_dqm_o),

	// Host Controller connections
	.do_mode_set(do_mode_set),
	.do_read(do_read),
    .do_write(do_write),
    .doing_refresh(doing_refresh),
    .sd_addx_mux(sd_addx_mux),
    .sd_addx10_mux(sd_addx10_mux),
    .sd_rd_ena(sd_rd_ena),
    .sd_data_ena(sd_dat_oe_o),
    .modereg_cas_latency(modereg_cas_latency),
    .modereg_burst_length(modereg_burst_length),
    .mp_data_mux(),
	.decoded_dqm(decoded_dqm),
    .do_write_ack(do_write_ack),
    .do_read_ack(do_read_ack),
    .do_modeset_ack(),
    .pwrup(pwrup),
    .busy(busy),
    .go(go),
    .refresh_timer_val(refresh_timer_val),
    .ras2cas_delay_val(ras2cas_delay_val),
    .refresh2anything_delay_val(refresh2anything_delay_val),
    .row_active_time_val(row_active_time_val),
    .last_data_in_to_row_precharge_val(last_data_in_to_row_precharge_val),
    .precharge_to_ras_val(precharge_to_ras_val),
    .do_refresh(do_refresh),
    .load_address(load_address),
    .load_data(load_data),
    .load_dqm(load_dqm),
    .assert_we(assert_we),

	// debug
    .next_state(),
	.autorefresh_cntr(),
	.autorefresh_cntr_l(),
	.cntr_limit()
);

sdram_dp i_sdram_dp
(
    .wb_clk_i(wb_clk_i),
    .mem_clk_i(mem_clk_i),
    .rst_i(wb_rst_i),

    // sdram state machine interface
    .do_mode_set(do_mode_set),
	.do_read(do_read),
    .do_write(do_write),
    .sd_addx_mux(sd_addx_mux),
    .sd_addx10_mux(sd_addx10_mux),
    .sd_rd_ena(sd_rd_ena),
    .decoded_dqm(decoded_dqm),
    .do_write_ack(do_write_ack),
    .do_read_ack(do_read_ack),
    .do_modeset_ack(1'b0),
    .pwrup(pwrup),

    // wishbone interface
    .wb_dat_i(wb_dat_i),
    .wb_dat_o(wb_dat_o),
    .wb_ack_o(wb_ack_o),
    .wb_sel_i(wb_sel_i),
    .wb_adr_i(wb_adr_i),
    .wb_we_i(wb_we_i),
    .wb_cyc_i(wb_cyc_i),
    .wb_stb_i(wb_stb_i),

    // sdram io interface
    .sd_adr_o(sd_adr_o),
    .sd_ba_o(sd_ba_o),
    .sd_dat_o(sd_dat_o),
    .sd_dat_i(sd_dat_i),

    // mode register settings
    .modereg_cas_latency(modereg_cas_latency),
    .modereg_burst_length(modereg_burst_length)
);

endmodule