sel.vhd

来自「可实现任意一位小数分频,在quartus II中仿真验证通过,输入端N为分频系数」· VHDL 代码 · 共 60 行

----------------------------------------------------------------------------------
-- Company: 		Hiline
-- Engineer: 		Liu Xiting
-- Email:			[e-mail];[e-mail]
-- 
-- Create Date:     21:13:54 01/03/2008 
-- Design Name: 	N.x frequency deviation
-- Module Name:		sel
-- Project Name:	NdotXfd
-- Target Devices:	EP1C6Q240C8 or other FPGA/CPLD Device
-- Tool versions: 	Quartus II 7.2
-- Description:		Judge to seletc N fd or N+1 fd
--					sel_out=1 to seletc N fd;
--					sel_out=0 to select N+1 fd;
--
-- Dependencies: 
--
-- Revision:		V1.0
--
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity sel is
	port
	(
		clock_in	: in std_logic;
		Xnumber		: in std_logic_vector(3 downto 0);
		sel_out		: out std_logic
	);
end entity;

architecture bhv of sel is

  signal XsubTen	: std_logic_vector(3 downto 0);
  signal q	 		: std_logic_vector(4 downto 0);

begin
  XsubTen <= 10 - Xnumber;
  sel: process(clock_in, q)
  begin
    if (clock_in'event and clock_in = '0') then
      if q + XsubTen >= 10 then
	    q <= q + XsubTen - 10;
	  else
	    q <= q + XsubTen;
	  end if;
	end if;
    if q >= Xnumber then
      sel_out <= '0';
	else
      sel_out <= '1';
    end if;
  end process sel;

end bhv;