cpcadd32.vhd

32位加法器组成原理课程设计

    LIBRARY IEEE;
      USE IEEE.STD_LOGIC_1164.ALL;
      USE  IEEE.STD_LOGIC_UNSIGNED.ALL;
      ENTITY cpcadd32 IS
      PORT(CI: IN STD_LOGIC;
            A: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
            B: IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
            S: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
            CO: OUT STD_LOGIC); 
        END cpcadd32;
        ARCHITECTURE TOP OF cpcADD32 IS
         COMPONENT cpcadd4
             PORT(CI: IN STD_LOGIC;
                   A: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
                   B: IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   S: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   M: OUT STD_LOGIC;
                   N: OUT  STD_LOGIC); 
               END  COMPONENT;
           COMPONENT bxjw
               PORT(CI: IN STD_LOGIC;
                     M3,M2,M1,M0: IN STD_LOGIC;
                     N3,N2,N1,N0: IN  STD_LOGIC;
                     C3,C2,C1,C0: OUT  STD_LOGIC); 
               
              END COMPONENT;
           SIGNAL   C3,C7,C11,C15,C19,C23,C27,C31,M8,M7,M6,M5,M4, M3,M2,M1,N8,N7,N6,N5,N4,N3,N2,N1:STD_LOGIC;
        BEGIN 
          U1:cpcadd4
              PORT  MAP(CI,A(3 DOWNTO 0 ),B(3 DOWNTO 0),S(3 DOWNTO 0 ),M8,N8);
          U2:cpcadd4
                PORT  MAP(C3,A(7  DOWNTO 4),B(7 DOWNTO 4),S(7 DOWNTO 4),M7,N7);
          U3:cpcadd4
              PORT  MAP(C7,A(11  DOWNTO 8),B(11 DOWNTO 8),S(11 DOWNTO 8),M6,N6);
          U4:cpcadd4
               PORT  MAP(C11,A(15  DOWNTO 12),B(15 DOWNTO 12),S(15 DOWNTO 12),M5,N5);
          U5:cpcadd4
                PORT  MAP(C15,A(19  DOWNTO 16),B(19 DOWNTO 16),S(19 DOWNTO 16),M4,N4);
          U6:cpcadd4
                PORT  MAP(C19,A(23  DOWNTO 20),B(23 DOWNTO 20),S(23 DOWNTO 20),M3,N3);
           U7:cpcadd4
                  PORT  MAP(C23,A(27  DOWNTO 24),B(27 DOWNTO 24),S(27 DOWNTO 24),M2,N2);
           U8:cpcadd4
                   PORT  MAP(C27,A(31 DOWNTO 28),B(31 DOWNTO 28),S(31 DOWNTO 28),M1,N1);
           U9:bxjw
                PORT MAP(CI,M8,M7,M6,M5,N8,N7,N6,N5,C3,C7,C11,C15)  ;                                                   
           U10:bxjw
                PORT MAP(C15,M4,M3,M2,M1,N4,N3,N2,N1,C19,C23,C27,C31); 
          CO<=C31;                                                    
       END TOP;