bxjw.vhd

来自「32位加法器组成原理课程设计」· VHDL 代码 · 共 17 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE  IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY bxjw IS
PORT(CI: IN STD_LOGIC;
       M3,M2,M1,M0: IN STD_LOGIC;
      N3,N2,N1,N0: IN  STD_LOGIC;
       C3,C2,C1,C0: OUT  STD_LOGIC); 
  END bxjw;
  ARCHITECTURE B OF bxjw IS
   BEGIN
    C3<=M3 OR (N3 AND CI);
   C2<=M2 OR(N2 AND M3)OR(N2 AND N3 AND CI);
   C1<=M1 OR (N1 AND M2)OR (N1 AND N2 AND M3)OR (N1 AND N2 AND N3 AND CI);
   C0<=M0 OR(N0 AND M1)OR (N0 AND N1 AND M2)OR (N0 AND N1 AND N2 AND M3)OR (N0 AND N1 AND N2 AND N3 AND CI) ;   
   END B;