cpcadd4.vhd

32位加法器组成原理课程设计

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE  IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cpcadd4 IS
PORT(CI: IN STD_LOGIC;
      A: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
      B: IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
      S: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
      M: OUT STD_LOGIC;
      N: OUT  STD_LOGIC); 
  END cpcadd4;
  ARCHITECTURE A OF cpcadd4 IS
      SIGNAL d: STD_LOGIC_VECTOR(3 DOWNTO 0);
      SIGNAL t:STD_LOGIC_VECTOR(3 DOWNTO 0);
       SIGNAL c2,c1,c0:std_logic;
       BEGIN
     d(0)<=A(0)AND B(0);
     t(0)<=A(0) OR  B(0);
     d(1)<=A(1) AND B(1);
    t(1)<=A(1) OR  B(1);
     d (2)<=A(2)  AND B(2);
     t(2)<=A(2) OR  B(2);
     d(3)<=A(3)  AND  B(3);
     t(3)<=A(3) OR  B(3);
     c0<=d(0) or (t(0)and ci);
      c1<=d(1) or (t(1) and d(0))or (t(1)and t(0) and ci);
     c2<=d(2)or (t(2) and d(1))or(t(2) and t(1)and d(0)) or (t(2)and t(1) and t(0) and ci);
          s(0)<= (NOT A(0)AND NOT B(0) AND CI)OR(NOT A(0)AND  B(0) AND NOT CI)OR( A(0)AND NOT B(0) AND  NOT CI)OR(A(0)AND B(0) AND CI) ; 
              s(1)<=(NOT A(1)AND NOT B(1) AND C0)OR(NOT A(1)AND  B(1) AND NOT C0)OR( A(1)AND NOT B(1) AND  NOT C0)OR(A(1)AND B(1) AND C0) ; 
              s(2)<=(NOT A(2)AND NOT B(2) AND C1)OR(NOT A(2)AND  B(2) AND NOT C1)OR( A(2)AND NOT B(2) AND  NOT C1)OR(A(2)AND B(2) AND C1) ; 
             s(3)<=(NOT A(3)AND NOT B(3) AND C2)OR(NOT A(3)AND  B(3) AND NOT C2)OR( A(3)AND NOT B(3) AND  NOT C2)OR(A(3)AND B(3) AND C2) ; 
         
         
 M<=d(3) or (t(3)and d(2))or (t(3)and t(2)and d(1))or(t(3) and t(2) and t(1)and d(0));
  N<=t(3)and t(2)and t(1)and t(0);       

        END A;